参数资料
| 型号： | X5043M8-2.7AT1 |
| 厂商： | Intersil |
| 文件页数： | 8/21页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU 4K EE 8-MSOP |
| 标准包装： | 2,500 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 2.92V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 带卷 (TR) |
X5043, X5045
SPI Serial Memory
V TRIP Programming
Execute
Reset V TRIP
Sequence
Set V CC = V CC Applied =
Desired V TRIP
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The array
is internally organized as 512 x 8 bits. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write ? cell,
providing a minimum endurance of 1,000,000 cycles and a
minimum data retention of 100 years.
New V CC Applied
=
Old V CC Applied
- Error
Execute
Set V TRIP
Sequence
New V CC Applied
=
Old V CC Applied
- Error
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device contains an 8-bit instruction register that controls
Apply 5V to V CC
Execute
Reset V TRIP
the operation of the device. The instruction code is written to
the device via the SI input. There are two write operations
Decrement V CC
(V CC = V CC –10mV)
Sequence
that requires only the instruction byte. There are two read
operations that use the instruction byte to initiate the output
of data. The remainder of the operations require an
instruction byte, an 8-bit address, then data bytes. All
instruction, address and data bits are clocked by the SCK
NO
RESET pin
goes active?
YES
input. All instructions (Table 1), addresses and data are
transferred MSB first.
Clock and Data Timing
Data input on the SI line is latched on the first rising edge of
Error ≤ -Emax
Measured V TRIP
-Desired V TRIP
Error ≥ Emax
SCK after CS goes LOW. Data is output on the SO line by
the falling edge of SCK. SCK is static, allowing the user to
stop the clock and then start it again to resume operations
-Emax < Error < Emax
where left off. CS must be LOW during the entire operation.
DONE
Emax = Maximum Desired Error
FIGURE 4. V TRIP PROGRAMMING SEQUENCE
TABLE 1. INSTRUCTION SET
INSTRUCTION NAME
WREN
WRDI
RSDR
WRSR
READ
WRITE
INSTRUCTION FORMAT*
0000 0110
0000 0100
0000 0101
0000 0001
0000 A 8 011
0000 A 8 010
OPERATION
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
Write Status Register (Watchdog and Block Lock)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)
Note:
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
8
FN8126.2
March 16, 2006
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