参数资料
| 型号： | A1425A-VQG100I |
| 厂商： | Microsemi SoC |
| 文件页数： | 5/90页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 2500 GATES 100-VQFP |
| 产品变化通告： | A1425A Family Discontinuation 23/Jan/2012 |
| 标准包装： | 90 |
| 系列： | ACT™ 3 |
| LAB/CLB数： | 310 |
| 输入/输出数： | 83 |
| 门数： | 2500 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-TQFP |
| 供应商设备封装： | 100-VQFP（14x14） |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页
Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 -5
Dedicated Clocks
Dedicated clock networks support high performance by providing sub-nanosecond skew and guaranteed
performance. Dedicated clock networks contain no programming elements in the path from the I/O Pad
Driver to the input of S-modules or I/O modules. There are two dedicated clock networks: one for the
array registers (HCLK), and one for the I/O registers (IOCLK). The clock networks are accessed by
special I/Os.
The routed clock networks are referred to as CLK0 and CLK1. Each network is connected to a clock
module (CLKMOD) that selects the source of the clock signal and may be driven as follows (Figure 2-6):
Externally from the CLKA pad
Externally from the CLKB pad
Internally from the CLKINA input
Internally from the CLKINB input
The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal
clock track are located in each horizontal routing channel. The function of the clock module is determined
by the selection of clock macros from the macro library. The macro CLKBUF is used to connect one of
the two external clock pins to a clock network, and the macro CLKINT is used to connect an internally
generated clock signal to a clock network. Since both clock networks are identical, the user does not care
whether CLK0 or CLK1 is being used. Routed clocks can also be used to drive high fanout nets like
resets, output enables, or data enables. This saves logic modules and results in performance increases
in some cases.
Routing Structure
The ACT 3 architecture uses vertical and horizontal routing tracks to connect the various logic and I/O
modules. These routing tracks are metal interconnects that may either be of continuous length or broken
into segments. Segments can be joined together at the ends using antifuses to increase their lengths up
to the full length of the track.
Figure 2-6
Clock Networks
CLKB
CLKA
FROM
PADS
CLOCK
DRIVERS
CLKMOD
CLKINB
CLKINA
S0
S1
INTERNAL
SIGNAL
CLKO(17)
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
CLOCK TRACKS
相关PDF资料 |
PDF描述 |
|---|---|
| A1425A-VQ100C | IC FPGA 2500 GATES 100-VQFP |
| IDT71V416S12BEG8 | IC SRAM 4MBIT 12NS 48FBGA |
| HMC65DRTS-S734 | CONN EDGECARD 130PS DIP .100 SLD |
| HMC65DRES-S734 | CONN EDGECARD 130PS .100 EYELET |
| AMC36DRXI-S734 | CONN EDGECARD 72POS DIP .100 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A1425LK | 功能描述:IC SENSOR HALL EFFECT AC 4-SIP RoHS:否 类别:传感器，转换器 >> 磁性 - 霍尔效应，数字式开关，线性，罗盘 (IC) 系列:- 标准包装:1 系列:- 传感范围:20mT ~ 80mT 类型:旋转 电源电压:4.5 V ~ 5.5 V 电流 - 电源:15mA 电流 - 输出（最大）:- 输出类型:数字式，PWM，8.5 位串行 特点:可编程 工作温度:-40°C ~ 150°C 封装/外壳:20-SSOP（0.209"，5.30mm 宽） 供应商设备封装:20-SSOP 包装:Digi-Reel® 其它名称:AS5132-HSST-500DKR |
| A1425LK-T | 功能描述:IC SENSOR HALL EFFECT AC 4-SIP RoHS:是 类别:传感器，转换器 >> 磁性 - 霍尔效应，数字式开关，线性，罗盘 (IC) 系列:- 标准包装:1 系列:- 传感范围:20mT ~ 80mT 类型:旋转 电源电压:4.5 V ~ 5.5 V 电流 - 电源:15mA 电流 - 输出（最大）:- 输出类型:数字式，PWM，8.5 位串行 特点:可编程 工作温度:-40°C ~ 150°C 封装/外壳:20-SSOP（0.209"，5.30mm 宽） 供应商设备封装:20-SSOP 包装:Digi-Reel® 其它名称:AS5132-HSST-500DKR |
| A1425-PQ160C | 制造商:Microsemi SOC Products Group 功能描述: |
| A1428AG1 | 制造商:DBLECTRO 制造商全称:DB Lectro Inc 功能描述:DIP PLUG PITCH:2.54mm |
| A1428AG2 | 制造商:DBLECTRO 制造商全称:DB Lectro Inc 功能描述:DIP PLUG PITCH:2.54mm |
发布紧急采购，3分钟左右您将得到回复。