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参数资料
型号： A3PN125-2VQ100
元件分类： FPGA
英文描述： FPGA, 3072 CLBS, 125000 GATES, PQFP100
封装： 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, VQFP-100
文件页数： 6/106页
文件大小： 3324K
代理商： A3PN125-2VQ100
ProASIC3 nano Flash FPGAs
R e visio n 8
4 -3
Revision 1
(continued)
The device architecture figures, Figure 1-3 ProASIC3 nano Device Architecture
Overview with Two I/O Banks (A3PN060 and A3PN125) through Figure 1-4
ProASIC3 nano Device Architecture Overview with Four I/O Banks (A3PN250),
were revised. Figure 1-1 ProASIC3 Device Architecture Overview with Two I/O
Banks and No RAM (A3PN010 and A3PN030) is new.
1-3
through
1-4
The "PLL and CCC" section was revised to include information about CCC-GLs in
A3PN020 and smaller devices.
1-6
Table 2-2 Recommended Operating Conditions 1, 2 was revised to add VMV to
the VCCI row. The following table note was added: "VMV pins must be connected
to the corresponding VCCI pins."
2-2
The values in Table 2-7 Quiescent Supply Current Characteristics were revised
for A3PN010, A3PN015, and A3PN020.
2-6
A table note, "All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide
range, as specified in the JESD8-B specification," was added to Table 2-14
Summary of Maximum and Minimum DC Input and Output Levels, Table 2-18
Summary of I/O Timing Characteristics—Software Default Settings (at 35 pF),
and Table 2-19 Summary of I/O Timing Characteristics—Software Default
Settings (at 10 pF).
2-16, 2-18
3.3 V LVCMOS Wide Range was added to Table 2-21 I/O Output Buffer
Maximum Resistances 1 and Table 2-23 I/O Short Currents IOSH/IOSL.
2-19, 2-20
The "48-Pin QFN" pin diagram was revised.
3-2
Note 2 for the "48-Pin QFN", "68-Pin QFN", and "100-Pin VQFP" pin diagrams
was added/changed to "The die attach paddle of the package is tied to ground
(GND)."
3-2, 3-5,
3-9
The "100-Pin VQFP" pin diagram was revised to move the pin IDs to the upper
left corner instead of the upper right corner.
3-9
Revision
Changes
Page
相关PDF资料
PDF描述
A3PN125-2VQG100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-2VQG100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQ100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQ100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQG100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
相关代理商/技术参数
参数描述
A3PN125-2VQ100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
A3PN125-2VQG100 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
A3PN125-2VQG100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
A3PN125-DIELOT 制造商:Microsemi Corporation 功能描述:A3PN125-DIELOT - Gel-pak, waffle pack, wafer, diced wafer on film
A3PN125-VQ100 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
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