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参数资料
型号： A54SX08A-2CQ208
厂商： Electronic Theatre Controls, Inc.
元件分类： FPGA
英文描述： SX-A Family FPGAs
中文描述： 的SX - A系列FPGA的
文件页数： 11/108页
文件大小： 720K
代理商： A54SX08A-2CQ208
SX-A Family FPGAs
v5.1
1-5
Clock Resources
Actel’s high-drive routing structure provides three clock
networks (
Table 1-1
). The first clock, called HCLK, is
hardwired from the HCLK buffer to the clock select
multiplexor (MUX) in each R-cell. HCLK cannot be
connected to combinatorial logic. This provides a fast
propagation path for the clock signal. If not used, this
pin must be set as Low or High on the board. It must not
be left floating.
Figure 1-7
describes the clock circuit
used for the constant load HCLK and the macros
supported.
HCLK does not function until the fourth clock cycle each
time the device is powered up to prevent false output
levels due to any possible slow power-on-reset signal and
fast start-up clock circuit. To activate HCLK from the first
cycle, the TRST pin must be reserved in the Design
software and the pin must be tied to GND on the board.
Two additional clocks (CLKA, CLKB) are global clocks that
can be sourced from external pins or from internal logic
signals within the SX-A device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB pins are not used or sourced from signals,
these pins must be set as Low or High on the board. They
must not be left floating.
Figure 1-8
describes the CLKA
and CLKB circuit used and the macros supported in SX-A
devices with the exception of A54SX72A.
In addition, the A54SX72A device provides four
quadrant clocks (QCLKA, QCLKB, QCLKC, and QCLKD—
corresponding to bottom-left, bottom-right, top-left,
and top-right locations on the die, respectively), which
can be sourced from external pins or from internal logic
signals within the device. Each of these clocks can
individually drive up to an entire quadrant of the chip,
or they can be grouped together to drive multiple
quadrants (
Figure 1-9 on page 1-6
). QCLK pins can
function as user I/O pins. If not used, the QCLK pins
must be tied Low or High on the board and must not be
left floating.
For more information on how to use quadrant clocks in
Global Clock Networks
in Actel’s Antifuse Device
s
and
RT54SX72S Quadrant Clocks
application notes.
The CLKA, CLKB, and QCLK circuits for A54SX72A as well
as the macros supported are shown in
Figure 1-10 on
page 1-6
. Note that bidirectional clock buffers are only
available in A54SX72A. For more information, refer to
the
"Pin Description" section on page 1-14
.
Table 1-1
SX-A Clock Resources
A54SX08A
A54SX16A
A54SX32A
A54SX72A
Routed Clocks (CLKA, CLKB)
2
2
2
2
Hardwired Clocks (HCLK)
1
1
1
1
Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD)
0
0
0
4
Figure 1-7
SX-A HCLK Clock Buffer
Figure 1-8
SX-A Routed Clock Buffer
Constant Load
Clock Network
HCLKBUF
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
相关PDF资料
PDF描述
A54SX16A-2CQ208 SX-A Family FPGAs
A54SX72A-2CQ208 SX-A Family FPGAs
A54SX32A-2CQ208 SX-A Family FPGAs
A54SX08A-2CQ208A SX-A Family FPGAs
A54SX16A-2CQ208A SX-A Family FPGAs
相关代理商/技术参数
参数描述
A54SX08A-2CQ208A 制造商:未知厂家 制造商全称:未知厂家 功能描述:SX-A Family FPGAs
A54SX08A-2CQ208B 制造商:未知厂家 制造商全称:未知厂家 功能描述:SX-A Family FPGAs
A54SX08A-2CQ208I 制造商:未知厂家 制造商全称:未知厂家 功能描述:SX-A Family FPGAs
A54SX08A-2CQ208M 制造商:未知厂家 制造商全称:未知厂家 功能描述:SX-A Family FPGAs
A54SX08A-2FG144 功能描述:IC FPGA SX 12K GATES 144-FBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:SX-A 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17）
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