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参数资料
型号： A54SX08A-2CQ208
厂商： Electronic Theatre Controls, Inc.
元件分类： FPGA
英文描述： SX-A Family FPGAs
中文描述： 的SX - A系列FPGA的
文件页数： 13/108页
文件大小： 720K
代理商： A54SX08A-2CQ208
SX-A Family FPGAs
v5.1
1-7
Other Architectural Features
Technology
The Actel SX-A family is implemented on a high-voltage,
twin-well CMOS process using 0.22
μ
/ 0.25
μ
design
rules. The metal-to-metal antifuse is comprised of a
combination of amorphous silicon and dielectric material
with barrier metals and has a programmed ('on' state)
resistance of 25
with capacitance of 1.0 fF for low
signal impedance.
Performance
The unique architectural features of the SX-A family
enable the devices to operate with internal clock
frequencies of 350 MHz, causing very fast execution of
even complex logic functions. The SX-A family is an
optimal platform upon which to integrate the
functionality previously contained in multiple complex
programmable logic devices (CPLDs). In addition, designs
that previously would have required a gate array to meet
performance goals can be integrated into an SX-A device
with dramatic improvements in cost and time-to-market.
Using timing-driven place-and-route tools, designers can
achieve highly deterministic device performance.
User Security
Reverse engineering is virtually impossible in SX-A
devices because it is extremely difficult to distinguish
between programmed and unprogrammed antifuses. In
addition, since SX-A is a nonvolatile, single-chip solution,
there is no configuration bitstream to intercept at device
power-up.
The Actel FuseLock advantage ensures that unauthorized
users will not be able to read back the contents of an
Actel antifuse FPGA. In addition to the inherent
strengths of the architecture, special security fuses that
prevent internal probing and overwriting are hidden
throughout the fabric of the device. They are located
where they cannot be accessed or bypassed without
destroying access to the rest of the device, making both
invasive and more-subtle noninvasive attacks ineffective
against Actel antifuse FPGAs.
Look for this symbol to ensure your valuable IP is secure
(
Figure 1-11
).
Implementation of
Security in Actel Antifuse FPGAs
I/O Modules
For a simplified I/O schematic, refer to Figure 1 in the
application note,
Actel eX, SX-A, and RTSX-S I/Os
.
Each user I/O on an SX-A device can be configured as an
input, an output, a tristate output, or a bidirectional pin.
Mixed I/O standards can be set for individual pins,
though this is only allowed with the same voltage as the
input. These I/Os, combined with array registers, can
achieve clock-to-output-pad timing as fast as 3.8 ns, even
without the dedicated I/O registers. In most FPGAs, I/O
cells that have embedded latches and flip-flops,
requiring instantiation in HDL code; this is a design
complication not encountered in SX-A FPGAs. Fast pin-
to-pin timing ensures that the device is able to interface
with any other device in the system, which in turn
enables parallel design of system components and
reduces overall design time. All unused I/Os are
configured as tristate outputs by the Actel Designer
software, for maximum flexibility when designing new
boards or migrating existing designs.
SX-A I/Os should be driven by high-speed push-pull
devices with a low-resistance pull-up device when being
configured as tristate output buffers. If the I/O is driven
by a voltage level greater than V
CCI
and a fast push-pull
device is NOT used, the high-resistance pull-up of the
driver and the internal circuitry of the SX-A I/O may
create a voltage divider. This voltage divider could pull
the input voltage below specification for some devices
connected to the driver. A logic '1' may not be correctly
presented in this case. For example, if an open drain
driver is used with a pull-up resistor to 5 V to provide the
logic '1' input, and V
CCI
is set to 3.3 V on the SX-A device,
the input signal may be pulled down by the SX-A input.
Each I/O module has an available power-up resistor of
approximately 50 k
that can configure the I/O in a
known state during power-up. For nominal pull-up and
pull-down resistor values, refer to
Table 1-4 on page 1-8
of the application note
Actel eX, SX-A, and RTSX-S I/Os
.
Just slightly before V
CCA
reaches 2.5 V, the resistors are
disabled, so the I/Os will be controlled by user logic. See
Table 1-2 on page 1-8
and
Table 1-3 on page 1-8
for
more information concerning available I/O features.
Figure 1-11
FuseLock
e
u
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相关代理商/技术参数
参数描述
A54SX08A-2CQ208A 制造商:未知厂家 制造商全称:未知厂家 功能描述:SX-A Family FPGAs
A54SX08A-2CQ208B 制造商:未知厂家 制造商全称:未知厂家 功能描述:SX-A Family FPGAs
A54SX08A-2CQ208I 制造商:未知厂家 制造商全称:未知厂家 功能描述:SX-A Family FPGAs
A54SX08A-2CQ208M 制造商:未知厂家 制造商全称:未知厂家 功能描述:SX-A Family FPGAs
A54SX08A-2FG144 功能描述:IC FPGA SX 12K GATES 144-FBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:SX-A 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17）
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