参数资料
型号: A54SX08A-2CQ208
厂商: Electronic Theatre Controls, Inc.
元件分类: FPGA
英文描述: SX-A Family FPGAs
中文描述: 的SX - A系列FPGA的
文件页数: 38/108页
文件大小: 720K
代理商: A54SX08A-2CQ208
SX-A Family FPGAs
2-18
v5.1
Timing Characteristics
Table 2-14
A54SX08A Timing Characteristics
(Worst-Case Commercial Conditions, V
CCA
= 2.25 V
,
V
CCI
= 3.0 V, T
J
= 70
°
C)
Parameter
Description
–2 Speed
–1 Speed
Std. Speed
–F Speed
Units
Min. Max. Min. Max.
Min.
Max.
Min. Max.
C-Cell Propagation Delays
1
t
PD
Predicted Routing Delays
2
Internal Array Module
0.9
1.1
1.2
1.7
ns
t
DC
FO = 1 Routing Delay, Direct Connect
0.1
0.1
0.1
0.1
ns
t
FC
FO = 1 Routing Delay, Fast Connect
0.3
0.3
0.4
0.6
ns
t
RD1
FO = 1 Routing Delay
0.3
0.4
0.5
0.6
ns
t
RD2
FO = 2 Routing Delay
0.5
0.5
0.6
0.8
ns
t
RD3
FO = 3 Routing Delay
0.6
0.7
0.8
1.1
ns
t
RD4
FO = 4 Routing Delay
0.8
0.9
1
1.4
ns
t
RD8
FO = 8 Routing Delay
1.4
1.5
1.8
2.5
ns
t
RD12
FO = 12 Routing Delay
2
2.2
2.6
3.6
ns
R-Cell Timing
t
RCO
Sequential Clock-to-Q
0.7
0.8
0.9
1.3
ns
t
CLR
Asynchronous Clear-to-Q
0.6
0.6
0.8
1.0
ns
t
PRESET
Asynchronous Preset-to-Q
0.7
0.7
0.9
1.2
ns
t
SUD
Flip-Flop Data Input Set-Up
0.7
0.8
0.9
1.2
ns
t
HD
Flip-Flop Data Input Hold
0.0
0.0
0.0
0.0
ns
t
WASYN
Asynchronous Pulse Width
1.4
1.5
1.8
2.5
ns
t
RECASYN
Asynchronous Recovery Time
0.4
0.4
0.5
0.7
ns
t
HASYN
Asynchronous Hold Time
0.3
0.3
0.4
0.6
ns
t
MPW
Clock Pulse Width
1.6
1.8
2.1
2.9
ns
Input Module Propagation Delays
t
INYH
Input Data Pad to Y High 2.5 V LVCMOS
0.8
0.9
1.0
1.4
ns
t
INYL
Input Data Pad to Y Low 2.5 V LVCMOS
1.0
1.2
1.4
1.9
ns
t
INYH
Input Data Pad to Y High 3.3 V PCI
0.6
0.6
0.7
1.0
ns
t
INYL
Input Data Pad to Y Low 3.3 V PCI
0.7
0.8
0.9
1.3
ns
t
INYH
Input Data Pad to Y High 3.3 V LVTTL
0.7
0.7
0.9
1.2
ns
t
INYL
Input Data Pad to Y Low 3.3 V LVTTL
1.0
1.1
1.3
1.8
ns
Notes:
1. For dual-module macros, use t
PD
+ t
RD1
+ t
PDn
, t
RCO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
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