参数资料
型号: A54SX08P-PQ208I
厂商: Electronic Theatre Controls, Inc.
英文描述: LM1881 Video Sync Separator; Package: SOIC NARROW; No of Pins: 8
中文描述: 54SX家庭的FPGA
文件页数: 12/57页
文件大小: 415K
代理商: A54SX08P-PQ208I
5 4 S X F a m ily F P G A s
12
v3.1
A 54S X 16P A C S pe c ific a tions for (P C I Ope ra tion)
Symbol
Parameter
Condition
0 < V
OUT
1.4
1
1.4
V
OUT
< 2.4
1, 2
Min.
Max.
Units
I
OH(AC)
Switching Current High
–44
mA
mA
–44 + (V
OUT
– 1.4)/0.024
3.1 < V
OUT
< V
CC1, 3
Equation A: on
page 13
–142
(Test Point)
V
OUT
= 3.1
3
V
OUT
2.2
1
2.2 > V
OUT
> 0.55
1
mA
mA
I
OL(AC)
Switching Current High
95
V
OUT
/0.023
0.71 > V
OUT
> 0
1, 3
Equation B: on
page 13
206
mA
(Test Point)
Low Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
V
OUT
= 0.71
3
–5 < V
IN
–1
0.4V to 2.4V load
4
2.4V to 0.4V load
4
mA
mA
V/ns
V/ns
I
CL
slew
R
slew
F
Notes:
1.
–25 + (V
IN
+ 1)/0.015
1
1
5
5
Refer to the V/I curves in
Figure8
. Switching current characteristics for REQ#and GNT#are permitted to be one half of that specified here;
i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#which are system outputs.
“Switching Current High” specification are not relevant to SERR# INTA# INTB# INTC# and INTD#which are open drain outputs.
Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward
the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.
Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B)
are provided with the respective diagrams in
Figure8
. The equation defined maxima should be met by design. In order to facilitate
component testing, a maximum current test point is defined for each side of the output driver.
This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point
within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an
unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is
now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to
revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard
designers must bear in mind that rise and fall times faster than this specification could occur, and should ensure that signal integrity
modeling accounts for this. Rise slew rate does not apply to open drain outputs.
2.
3.
4.
output
buffer
1/2 in. max.
V
CC
1k
10 pF
1k
pin
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A54SX08-PQ208I 功能描述:IC FPGA SX 12K GATES 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:SX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA(27X27)
A54SX08-PQ208M 制造商:未知厂家 制造商全称:未知厂家 功能描述:54SX Family FPGAs