参数资料
型号: SC16C650BIB48,128
厂商: NXP Semiconductors
文件页数: 3/48页
文件大小: 0K
描述: IC UART SOT313-2
标准包装: 2,000
通道数: 1,UART
FIFO's: 32 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 带卷 (TR)
其它名称: 935274391128
SC16C650BIB48-F
SC16C650BIB48-F-ND
SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
11 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
In the event that the receive buffer is overlling and ow control needs to be executed, the
SC16C650B automatically sends an Xoff message (when enabled) via the serial TX
output to the remote modem. The SC16C650B sends the Xoff1/Xoff2 characters as soon
as received data passes the programmed trigger level. To clear this condition, the
SC16C650B will transmit the programmed Xon1/Xon2 characters as soon as receive data
drops below the next low or programmed trigger level.
6.5 Special feature software ow control
A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit
character is detected, it will be placed on the user-accessible data stack along with normal
incoming RX data. This condition is selected in conjunction with EFR[3:0]. Note that
software ow control should be turned off when using this special mode by setting
EFR[3:0] to a logic 0.
The SC16C650B compares each incoming receive character with Xoff2 data. If a match
exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate
detection of a special character. Although Table 8 “SC16C650B internal registers” shows
each X-register with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register bits LCR[1:0] dene the
number of character bits, i.e., either 5 bits, 6 bits, 7 bits or 8 bits. The word length selected
by LCR[1:0] also determine the number of bits that will be used for the special character
comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive character.
6.6 Hardware/software and time-out interrupts
Three special interrupts have been added to monitor the hardware and software ow
control. The interrupts are enabled by IER[7:5]. Care must be taken when handling these
interrupts. Following a reset, the transmitter interrupt is enabled, the SC16C650B will
issue an interrupt to indicate that the Transmit Holding Register is empty. This interrupt
must be serviced prior to continuing operations. The ISR register provides the current
singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have
lowest interrupt priority. A condition can exist where a higher priority interrupt may mask
the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt
will the lower priority CTS/RTS interrupt(s) be reected in the status register. Servicing the
interrupt without investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C650B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive
Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the
center of each stop bit received or each time the Receive Holding Register (RHR) is read.
The actual time-out value is 4 character time.
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