参数资料
型号: TMS320C6415TBGLZA6
厂商: Texas Instruments
文件页数: 21/146页
文件大小: 0K
描述: IC FIXED-POINT DSP 532-FCBGA
标准包装: 60
系列: TMS320C6414T/15T/16T
类型: 定点
接口: 主机接口,McBSP,PCI,UTOPIA
时钟速率: 600MHz
非易失内存: 外部
芯片上RAM: 1.03MB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.10V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 532-BFBGA,FCBGA
供应商设备封装: 532-FCBGA(23x23)
包装: 托盘
配用: TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
117
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING
timing requirements for McBSP (see Figure 51)
NO.
600
720
850
1G
UNIT
MIN
MAX
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
4P or 6.67§
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
0.5tc(CKRX) 1#
ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int
9
ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR ext
1.3
ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int
6
ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR ext
3
ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int
8
ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR ext
0.9
ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int
3
ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR ext
3.1
ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int
9
ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX ext
1.3
ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int
6
ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX ext
3
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based
on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
Use whichever value is greater.
# This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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