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| 型号： | LT1768IGN#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR CCFL SGL/MULT HP 16SSOP |
| 标准包装： | 2,500 |
| 类型： | CCFL 控制器 |
| 频率： | 300 ~ 410 kHz |
| 电流 - 电源： | 7mA |
| 电流 - 输出： | 1.5A |
| 电源电压： | 9 V ~ 24 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 带卷 (TR) |
LT1768
APPLICATIO N S I N FOR M ATIO N
voltage and DIO lines can cause enough current flow to
fool the open lamp detection. In situations where coupling
can’t be avoided, resistors can be added from the DIO pins
to ground to increase the open lamp threshold. When
resistors from the DIO pins to ground are added, the
values for R RMAX and R RMIN may need to be increased
from their nominal values to compensate for the additional
current.
For single lamp operation, the lowside of the lamp should
be connected to both DIO pins, and the values of R RMAX
and R RMIN increased to two times the values that would be
used in a dual lamp configuration. In single lamp mode all
fault detection will operate as in the dual lamp configura-
tion, but the open lamp threshold will double. If the
increase in the open lamp threshold is not acceptable, a
positive offset current can be added to reduce the open
lamp threshold by placing a resistor between the REF and
DIO pins (a 33k resistor will reduce the open lamp thresh-
old by approximately 100 μ A ((V REF – V DIO+ )/33k). When
an offset current is added, the values for R RMAX and R RMIN
may need to be increased from their nominal values to
compensate for the offset current.
VC Compensation
As previously mentioned a single capacitor on the VC pin
combines the error signal conversion, lamp current aver-
aging and frequency compensation. Careful consideration
should be given to the value of capacitance used. A large
value (1 μ F) will give excellent stability at high lamp cur-
rents but will result in degraded line regulation in PWM
mode. On the other hand , a small value (10nF) will give
excellent PWM response but might result in overshoot and
poor load regulation. The value chosen will depend on the
maximum load current and dimming range. After these
parameters are decided upon, the value of the VC capacitor
should be increased until the line regulation becomes
start of every oscillator cycle. The GATE is driven back low
when the current reaches a threshold level proportional to
the voltage on the VC pin. The GATE then remains low until
the start of the next oscillator cycle. The peak current is
thus proportional to the VC voltage and controlled on a
cycle by cycle basis. The peak switch current is normally
sensed by placing a sense resistor in the source lead of the
output MOSFET. This resistor converts the switch current
to a voltage that can be compared to a fraction of the VC
voltage [(V VC – V DIODE )/30] . For normal conditions and a
GATE duty cycle below 50%, the switch current limit will
correspond to I PK = 0.1/R SENSE . For GATE duty cycles
above 50% the switch current limit will be reduced
to approximately 90mV at 80% duty cycle to avoid
subharmonic oscillations associated with current mode
controllers.
When the lamp current is programmed to PWM mode, the
VC pin will slew between voltages that represent the
minimum and maximum PWM lamp currents. The slew
time affects the line regulation at low duty cycle, and
should be kept low by making the sense resistor as small
as possible. The lowest value of sense resistor is deter-
mined by switching transients and other noise due to
layout configurations. A good rule of thumb is to set the
sense resistor so that the voltage on the VC pin equals
2.5V when the PWM current is in maximum mode (V PROG
= V PWM ). Typical values of the sense resistor run in the
25m ? to 50m ? range for large displays, and can be
implemented with a copper trace on the PCB.
Since the maximum threshold at the SENSE pin is only
100mV, switching transients and other noise can prema-
turely trip the comparator. The LT1768 has a blanking
period of 100ns which prohibits premature switch turn
off, but further filtering the sense resistor voltage is
recommended. A simple RC filter is adequate for most
applications. (Figure 5.)
unacceptable. A typical value for the VC capacitor is
0.033 μ F. For further information on compensation please
refer to the references or consult the factory.
LT1768
GATE
100 ?
SENSE
Current Sense Comparator
2.2nF
0.025m ?
The LT1768 is a current mode PWM controller. Under
normal operating conditions the GATE is driven high at the
Figure 5. Sense Pin Filter
1768 ?F05
13
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相关代理商/技术参数 |
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| AD5282BRU200 | 功能描述:IC DUAL POT 200K 256POS 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 标准包装:3,000 系列:DPP 接片:32 电阻（欧姆）:10k 电路数:1 温度系数:标准值 300 ppm/°C 存储器类型:非易失 接口:3 线串行（芯片选择，递增，增/减） 电源电压:2.5 V ~ 6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 供应商设备封装:8-TDFN（2x3） 包装:带卷 (TR) |
| AD5282BRU200-REEL7 | 功能描述:IC DGTL POT DUAL 256POS 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 标准包装:3,000 系列:DPP 接片:32 电阻（欧姆）:10k 电路数:1 温度系数:标准值 300 ppm/°C 存储器类型:非易失 接口:3 线串行（芯片选择，递增，增/减） 电源电压:2.5 V ~ 6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 供应商设备封装:8-TDFN（2x3） 包装:带卷 (TR) |
| AD5282BRU20-REEL7 | 制造商:Analog Devices 功能描述:DGTL POTENTIOMETER 256POS 20KOHM DUAL 16TSSOP - Tape and Reel |
| AD5282BRU20Z | 制造商:Analog Devices 功能描述:DIG POT 2CH 256 20KOHM 14TSSOP 制造商:Analog Devices 功能描述:DIG POT, 2CH, 256, 20KOHM, TSSOP-16 制造商:Analog Devices 功能描述:DIG POT, 2CH, 256, 20KOHM, 14TSSOP 制造商:Analog Devices 功能描述:DIG POT, 2CH, 256, 20KOHM, 14TSSOP, End To End Resistance:20kohm, Track Taper:Li 制造商:Analog Devices 功能描述:DIG POT, 2CH, 256, 20KOHM, 14TSSOP, End To End Resistance:20kohm, Track Taper:Linear, Resistance Tolerance: 30%, Supply Voltage Min:4.5V, Supply Voltage Max:16.5V, Potentiometer IC Case Style:TSSOP, No. of Pins:16, No. of Steps:256, , RoHS Compliant: Yes |
| AD5282BRU50 | 功能描述:IC DUAL POT 50K 256POS 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 标准包装:3,000 系列:DPP 接片:32 电阻（欧姆）:10k 电路数:1 温度系数:标准值 300 ppm/°C 存储器类型:非易失 接口:3 线串行（芯片选择，递增，增/减） 电源电压:2.5 V ~ 6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 供应商设备封装:8-TDFN（2x3） 包装:带卷 (TR) |
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