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| 型号： | LT1768IGN#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/20页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR CCFL SGL/MULT HP 16SSOP |
| 标准包装： | 2,500 |
| 类型： | CCFL 控制器 |
| 频率： | 300 ~ 410 kHz |
| 电流 - 电源： | 7mA |
| 电流 - 输出： | 1.5A |
| 电源电压： | 9 V ~ 24 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 带卷 (TR) |
LT1768
PI N FU N CTIO N S
PGND (Pin 1): The PGND pin is the high current ground
path. High switching current transients and lamp current
flow through the PGND pin.
DIO1/DIO2 (Pins 3/2): Each DIO pin is the common
connection between the cathode and anode of two internal
diodes. The remaining terminals of the diodes are con-
nected to PGND. In a typical application, the DIO1/2 pins
are connected to the low voltage side of the lamps.
Bidirectional lamp current flows into the DIO1/2 pins and
their diodes conduct alternately on the half cycles. The
diode that conducts on the negative cycle has a percentage
of its current diverted into the VC pin. This current nulls
against the programming current specified by the PROG
and PWM pins. A single capacitor on the VC pin provides
both stable loop compensation and an averaging function
to the half wave-rectified lamp current. The diode that
conducts on the positive cycle is used to detect open lamp
conditions. If the current in either of the DIO pins on the
positive cycle is less than 125 μ A for a minimum of 1 PWM
cycle, then the FAULT pin will be activated and the maxi-
mum source current into the VC pin will be reduced by
approximately 50%. If the current in both of the DIO pins
on the positive cycle is less than 125 μ A, and the VC pin hits
its clamp value (indicating either an open lamp or lamp
lowside short to ground fault condition) for a minimum of
1 PWM cycle, the gate drive will be latched off. The latch
can be cleared by setting the PROG voltage to zero or
provides lamp current averaging and single pole loop
compensation.
AGND (Pin 6): The AGND pin is the low current analog
ground. It is the negative sense terminal for the internal
reference and current sense amplifier. Connect critical
external components that terminate to ground directly to
this pin for best performance.
C T (Pin 7): The value of capacitance on the C T pin deter-
mines the PWM modulation frequency. The transfer func-
tion of capacitance to frequency equals 22Hz/C T ( μ F). The
frequency present on the C T pin also determines the
maximum time allowed for lamp fault conditions. If the
current in either DIO1 or DIO2 is less than 125 μ A for a
minimum of 1 PWM period, the FAULT pin is activated and
the maximum allowable lamp current is reduced by ap-
proximately 50%. If the current in both DIO1 and DIO2 is
absent for a minimum of 1 PWM period, and the VC pin is
clamped at 3.7V, the FAULT pin is activated and the gate
drive of the part is internally latched off. The latch can be
cleared by setting the PROG voltage to zero or placing the
LT1768 in shutdown mode.
PROG (Pin 8): The PROG pin controls the lamp current by
converting a DC input voltage range of 0V to 5V to source
current into the VC pin. The transfer function from pro-
gramming voltage to VC current is illustrated in the follow-
ing table.
placing the LT1768 in shutdown mode.
SENSE (Pin 4): The SENSE pin is the input to the current
sense comparator. The threshold of the comparator is a
function of the voltage on the VC pin and the switch duty
cycle. The maximum threshold is set at 100mV for duty
cycle less than 50% which corresponds to approximately
PROG (V)
V PROG < 0.5
0.5 < V PROG < 1.0
1.0 < V PROG < V PWM
V CT > V PROG
V CT < V PROG
VC SOURCE CURRENT ( μ A)
0
I RMIN
PWM Mode*
I RMIN
5 ? I RMAX ? ( V PWM – 1V)/ 3V
3.7V on the VC pin. The SENSE pin has a bias current of
25 μ A, which flows out of the pin.
VC (Pin 5): The VC pin is the summing junction for the
programming current and the half wave rectified lamp
current and is also an input to the current sense compara-
tor . A fraction of the voltage on the VC pin is compared to
the voltage on the SENSE pin (switch current) for switch
turnoff. During normal operation the VC pin sits between
0.7V (zero switch current) and 3.7V (maximum switch
current). A single capacitor between VC and AGND
V PROG > 4.0 5 ? I RMAX
*PWM Duty Cycle = [1 – (V PWM – V PROG )/(V PWM – 1V)] ? 100%
PWM (Pin 9): The PWM pin controls the percentage of the
PROG range between 1V and 4V that is to be pulse width
modulated. The percentage is defined by [(V PWM -1)/ 3] ?
100%. The minimum and maximum percentages are 25%
(1.75V) and 100% (4V) respectively. Taking the PWM pin
above the 4V maximum will cause significant PWM input
current to flow. (See PWM Input Current vs Voltage curve
in Typical Performance Characteristics).
7
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