参数资料
型号: IDT70V657S12BF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 6/24页
文件大小: 0K
描述: IC SRAM 1.125MBIT 12NS 208FBGA
标准包装: 1,000
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 1.125M(32K x 36)
速度: 12ns
接口: 并联
电源电压: 3.15 V ~ 3.45 V
工作温度: 0°C ~ 70°C
封装/外壳: 208-LFBGA
供应商设备封装: 208-CABGA(15x15)
包装: 带卷 (TR)
其它名称: 70V657S12BF8
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Pin Names
Industrial and Commercial Temperature Ranges
A 0L - A 16L
A 0R - A 16R
Left Port
CE 0L , CE 1L
R/ W L
OE L
(3)
I/O 0L - I/O 35L
SEM L
INT L
BUSY L
BE 0L - BE 3L
V DDQL
OPT L
Right Port
CE 0R , CE 1R
R/ W R
OE R
(3)
I/O 0R - I/O 35R
SEM R
INT R
BUSY R
BE 0R - BE 3R
V DDQR
OPT R
M/ S
V DD
Names
Chip Enables - (Input)
Read/Write Enable - (Input)
Output Enable - (Input)
Address - (Input)
Data Input/Output
Semaphore Enable - (Input)
Interrupt Flag - (Output)
Busy Flag - (Output) (4)
Byte Enables (9-bit bytes) - (Input)
Power (I/O Bus) (3.3V or 2.5V) - (Input) (1)
Option for selecting V DDQX - (Input) (1,2)
Master or Slave Select - (Input)
Power (3.3V) - (Input) (1)
V SS
TDI
TDO
TCK
TMS
TRST
Ground (0V) - (Input)
Test Data Input
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
Reset (Initialize TAP Controller)
4869 tbl 01
6
NOTES:
1. V DD , OPT X , and V DDQX must be set to appropriate operating levels prior to
applying inputs on I/O X .
2. OPT X selects the operating voltage levels for the I/Os and controls on that port.
If OPT X is set to V IH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V DDQX must be supplied at 3.3V. If OPT X is set to V IL (0V), then that
port's I/Os and controls will operate at 2.5V levels and V DDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
3. Addresses A 16 x is a NC for IDT70V658. Also, Addresses A 16 x and A 15 x are
NC's for IDT70V657.
4. BUSY is an input as a slave (M/ S = V IL ).
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