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参数资料
| 型号： | AD7441BRTZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/25页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT W/DIFF INP SOT-23-8 |
| 标准包装： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 9.25mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-8 |
| 供应商设备封装： | SOT-23-8 |
| 包装： | 标准包装 |
| 输入数目和类型： | 1 个伪差分，单极 |
| 其它名称： | AD7441BRTZ-REEL7DKR |
AD7441/AD7451
Rev. D | Page 13 of 24
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7441/AD7451 are 10-/12-bit, high speed, low power,
single-supply, successive approximation, analog-to-digital con-
verters (ADCs) with a pseudo differential analog input. These
parts operate with a single 2.7 V to 5.25 V power supply and are
capable of throughput rates up to 1 MSPS when supplied with
an 18 MHz SCLK. The AD7441/AD7451 require an external
reference to be applied to the VREF pin.
The AD7441/AD7451 have a SAR ADC, an on-chip differential
track-and-hold amplifier, and a serial interface housed in either
an 8-lead SOT-23 or an MSOP package. The serial clock input
accesses data from the part and provides the clock source for
the SAR ADC. The AD7441/AD7451 feature a power-down
option for reduced power consumption between conversions.
The power-down feature is implemented across the standard
serial interface, as described in the Modes of Operation section.
CONVERTER OPERATION
The AD7441/AD7451 are SAR ADCs based around two
schematics of the ADC in the acquisition and conversion phase,
respectively. The ADC is comprised of control logic, an SAR,
and two capacitive DACs. In Figure 19 (acquisition phase), SW3
is closed, SW1 and SW2 are in Position A, the comparator is
held in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
VIN+
VIN–
A
B
SW1
SW3
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
CAPACITIVE
DAC
CS
VREF
SW2
B
A
03
15
3-
0
19
Figure 19. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 20), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribu-
tion DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The control logic generates
the ADC output code. The output impedances of the sources
driving the VIN+ and VIN– pins must be matched; otherwise the
two inputs have different settling times, resulting in errors.
VIN+
VIN–
A
B
SW1
SW3
COMPARATOR
CONTROL
LOGIC
CAPACITIVE
DAC
CAPACITIVE
DAC
CS
VREF
SW2
B
A
03
15
3-
0
20
Figure 20. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7441/AD7451 is straight (natural)
binary. The designed code transitions occur at successive LSB
values (1 LSB, 2 LSB, and so on). The LSB size of the AD7451
is VREF/4096, and the LSB size of the AD7441 is VREF/1024. The
ideal transfer characteristic of the AD7441/AD7451 is shown in
000...000
0V
A
D
C
CO
DE
ANALOG INPUT
111...111
000...001
111...000
011...111
111...110
000...010
1LSB = VREF/4096 (AD7451)
1LSB = VREF/1024 (AD7441)
VREF – 1LSB
1LSB
03
15
3-
0
21
Figure 21. AD7441/AD7451 Ideal Transfer Characteristic
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