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参数资料
| 型号： | LTC4253AIGN#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 21/34页 |
| 文件大小： | 383K |
| 描述： | IC HOT SWAP CONTRLR -48V 16-SSOP |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 8.2 V ~ 14.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 带卷 (TR) |
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LTC4253/LTC4253A
21
425353aff
For more information www.linear.com/4253
Computing the maximum soft-start capacitor value during
soft-start to a load short is complicated by the nonlinear
MOSFETs SOA characteristics and the R
SS
C
SS
response.
An overconservative but simple approach begins with the
maximum circuit breaker current, given by:
I
CB(MAX)
=
V
CB(MAX)
R
S
(14)
where V
CB(MAX)
is 60mV (55mV for the LTC4253A).
From the SOA curves of a prospective MOSFET , determine
the time allowed, t
SOA(MAX)
. C
SS
is given by:
C
SS
=
t
SOA(MAX)
0.916 R
SS
for the LTC4253
C
SS
=
t
SOA(MAX)
2.48 R
SS
for the LTC4253A
(15)
In the above example, 60mV/40m?gives 1.5A. t
SOA
for
the IRF530S is 40ms. From Equation (15), C
SS
= 437nF .
Actual board evaluation showed that C
SS
= 100nF was ap-
propriate. The ratio ( R
SS
"
C
SS
) to t
CL(CHARGE)
is a good
gauge as large ratios may result in the time-out period
expiring prematurely. This gauge is determined empirically
with board level evaluation.
SUMMARY OF DESIGN FLOW
To summarize the design flow, consider the application
shown in Figure 3 for the LTC4253A. It was designed for
80W and C
L
??00礔 .
Calculate maximum load current: 80W/43V = 1.86A;
allowing for 83% converter efficiency, I
IN(MAX)
= 2.2A.
Calculate R
S
: from Equation (8) R
S
= 20m?
Calculate I
SHORT-CIRCUIT(MAX)
: from Equation (10)
I
SHORTCIRCUIT(MAX)
= 3.3A.
Select a MOSFET that can handle 3.3A at 71V: IRF530S.
Calculate C
T
: from Equation (13) C
T
= 302nF . Select
C
T
?=?680nF , which gives the circuit breaker time-out
period t
MAX
= 5.9ms.
Consult MOSFET SOA curves: the IRF530S can handle 3.3A
at 100V for 8.3ms, so it is safe to use in this application.
Calculate C
SS
: using Equations (14) and (15) select
C
SS
??3nF .
FREQUENCY COMPENSATION
The LTC4253 typical frequency compensation network
for the analog current limit loop is a series R
C
(10?
and C
C
connected from GATE to V
EE
. Figure 6 depicts the
relationship between the compensation capacitor C
C
and
the MOSFETs C
ISS
. The line in Figure 6 is used to select
a starting value for C
C
based upon the MOSFETs C
ISS
specification. Optimized values for C
C
are shown for sev-
eral popular MOSFETs. Differences in the optimized value
of C
C
versus the starting value are small. Nevertheless,
compensation values should be verified by board level
short-circuit testing.
As seen in Figure 5, at the onset of a short-circuit event,
the input supply voltage can ring dramatically due to series
inductance. If this voltage avalanches the MOSFET , current
continues to flow through the MOSFET to the output. The
analog current limit loop cannot control this current flow
and therefore the loop undershoots. This effect cannot be
eliminated by frequency compensation. A Zener diode is
required to clamp the input supply voltage and prevent
MOSFET avalanche.
Figure 6. Recommended Compensation
Capacitor C
C
vs MOSFET C
ISS
for the LTC4253
MOSFET C
ISS
(pF)
4253 F06
60
50
40
30
20
10
0
0
2000
4000
6000
8000
IRF530
IRF540
IRF740
IRF3710
NTY100N10
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