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参数资料
| 型号： | MAX6971AUG+ |
| 厂商： | Maxim Integrated |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVER LINEAR 24-TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 62 |
| 恒定电流： | 是 |
| 拓扑： | 线性，高端 |
| 输出数： | 16 |
| 内部驱动器： | 是 |
| 类型 - 主要： | LED 照明显示器，标牌，汽车 |
| 电源电压： | 3 V ~ 5.5 V |
| 输出电压： | 36V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 管件 |
| 工作温度： | -40°C ~ 125°C |
16-Port, 36V Constant-Current LED Driver
CLK is the serial-clock input, which shifts data at DIN
into the MAX6971 16-bit shift register on its rising edge.
LE
OUT_
LE
OUT_
t LRF
t LRR
LE is the latch load input of the MAX6971 that transfers
data from the MAX6971 16-bit shift register to its 16-bit
latch when LE is high (transparent latch), and latches
the data on the falling edge of LE (Figure 2).
The fourth input provides output-enable control of the
output drivers. OE is high to force outputs
OUT0 –OUT15 high impedance, without altering the
contents of the output latches, and low to enable out-
puts OUT0 –OUT15 to follow the state of the output
latches.
CLK
OUT_
t CRF
OE is independent of the operation of the serial inter-
face. Data can be shifted into the serial-interface shift
register and latched, regardless of the state of OE .
DOUT is the serial-data output, which shifts data out
CLK
t CRR
from the MAX6971’s 16-bit shift register on the rising
edge of CLK. Data at DIN is propagated through the
shift register and appears at DOUT 16 clock cycles later.
OUT_
Figure 3. LE and CLK to OUT_ Timing
Table 1. 4-Wire Serial-Interface Truth Table
SERIAL
DATA
INPUT
DIN
CLOCK
INPUT
CLK
D 0
SHIFT-REGISTER
CONTENTS
D 1 D 2 … D n-1 D n
LOAD
INPUT
LE
D 0
LATCH CONTENTS
D 1 D 2 … D n-1 D n
BLANKING
INPUT
OE
D 0
OUTPUT CONTENTS
D 1 D 2 … D n-1 D n
H
L
X
H
L
R 0
R 1
R 1
R 1
R 2
R 2
R 2
… R n-2 R n-1
… R n-2 R n-1
… R n-1 R n
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
…
X
X
H
R 0
R 1
R 2
— R n-1 R n
—
—
—
—
—
—
—
—
—
P 1
P 2
P 3
… P n-1 P n
L
P 0
P 1
P 2
… P n-1 P n
L
P 0
P 1
P 2
… P n - 1 P n
—
—
—
—
—
— — —
—
X
X
X
…
X
X
H
Hi-Z Hi-Z Hi-Z … Hi-Z Hi-Z
L = Low-logic level.
H = High-logic level.
X = Don’t care.
P = Present state.
R = Previous state.
Hi-Z = High impedance.
8
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