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参数资料
| 型号： | LTC3209EUF-1#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVR QVGA DISPLAY 20-QFN |
| 标准包装： | 2,500 |
| 拓扑： | 升压（升压），切换式电容器（充电泵） |
| 输出数： | 8 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光 |
| 类型 - 次要： | 白色 LED |
| 频率： | 850kHz |
| 电源电压： | 2.9 V ~ 4.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN 裸露焊盘（4x4） |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 85°C |
LTC3209-1/LTC3209-2
APPLICATIO S I FOR ATIO
lose considerable capacitance over that range. Z5U and
Y5V capacitors may also have a very poor voltage
coefficient causing them to lose 60% or more of their
capacitance when the rated voltage is applied. Therefore,
when comparing different capacitors, it is often more
appropriate to compare the amount of achievable
capacitance for a given case size rather than comparing
the specified capacitance value. For example, over rated
voltage and temperature conditions, a 1 μ F, 10V, Y5V
ceramic capacitor in a 0603 case may not provide any
more capacitance than a 0.22 μ F, 10V, X7R available in the
same case. The capacitor manufacturer’s data sheet
should be consulted to determine what value of capacitor
is needed to ensure minimum capacitances at all
temperatures and voltages.
Table 1 shows a list of ceramic capacitor manufacturers
and how to contact them:
Table 1. Recommended Capacitor Vendors
The following guidelines should be followed when design-
ing a PCB layout for the LTC3209.
? The Exposed Pad should be soldered to a large copper
plane that is connected to a solid, low impedance ground
plane using plated, through-hole vias for proper heat
sinking and noise protection.
? Input and output capacitors (C1 and C4) must be placed
close to the part.
? The flying capacitors (C2 and C3) must be placed close
to the part. The traces running from the pins to the
capacitor pads should be as wide as possible.
? V BAT , CPO traces must be made wide to minimize
inductance and handle the high currents.
? LED pads must be large and connected to other layers of
metal to ensure proper heat sinking.
AVX
www.avxcorp.com
ALL VIAS
LABELED V BAT
Kemet
Murata
Taiyo Yuden
Vishay
www.kemet.com
www.murata.com
www.t-yuden.com
www.vishay.com
GND
PLANE
LAYER
C2
C3
ARE CONNECTED TO
V BAT PLANE LAYER
V BAT ALL VIAS
LABELED GND
ARE CONNECTED TO
GND PLANE LAYER
Layout Considerations and Noise
Due to the high switching frequency and the transient
currents produced by the LTC3209-1/LTC3209-2, careful
GND
C4
CPO
V BAT1
C1
GND
SOLDER SIDE
COMPONENT
board layout is necessary. A true ground plane and short
connections to all capacitors will improve performance
and ensure proper regulation under all conditions.
GND
DV CC
The flying capacitor pins C1P, C2P, C1M and C2M will
R REF
C5
have high edge rate waveforms. The large dv/dt on these
pins can couple energy capacitively to adjacent PCB runs.
Magnetic fields can also be generated if the flying capaci-
V BAT PLANE
LAYER
V BAT
V BAT2
C6
R1
GND
tors are not close to the LTC3209-1/LTC3209-2 (i.e., the
loop area is large). To decouple capacitive energy transfer,
a Faraday shield may be used. This is a grounded PCB
GND
GND
trace between the sensitive node and the LTC3209-1/
LTC3209-2 pins. For a high quality AC ground, it should be
Figure 7. PC Board Layout Example (LTC3209-1)
3209 F07
returned to a solid ground plane that extends all the way to
the LTC3209-1/LTC3209-2.
320912fa
17
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