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参数资料
| 型号： | MC100EP05MNR4G |
| 厂商： | ON Semiconductor |
| 文件页数： | 1/11页 |
| 文件大小： | 0K |
| 描述： | IC GATE AND/NAND 2INP DIFF 8-DFN |
| 标准包装： | 1,000 |
| 系列： | 100EP |
| 逻辑类型： | 与/与非门 |
| 电路数： | 1 |
| 输入数： | 2 输入（1，1） |
| 施密特触发器输入： | 无 |
| 输出类型： | 差分 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-VFDFN 裸露焊盘 |
| 供应商设备封装： | 8-DFN（2x2） |
| 包装： | 带卷 (TR) |
Semiconductor Components Industries, LLC, 2008
August, 2008 Rev. 9
1
Publication Order Number:
MC10EP05/D
MC10EP05, MC100EP05
3.3V / 5VECL 2-Input
Differential AND/NAND
Description
The MC10/100EP05 is a 2input differential AND/NAND gate.
The device is functionally equivalent to the EL05 and LVEL05
devices. With AC performance much faster than the LVEL05 device,
the EP05 is ideal for applications requiring the fastest
AC performance available.
The 100 Series contains temperature compensation.
Features
220 ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 3.0 V to 5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at VEE
PbFree Packages are Available
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
H
= MC10
K
= MC100
5I
= MC10
2X
= MC100
D
= Date Code
SOIC8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
TSSOP8
DT SUFFIX
CASE 948R
ALYWG
G
HP05
ALYWG
G
KP05
1
8
1
8
1
8
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
1
8
HEP05
ALYWG
G
1
8
KEP05
ALYWG
G
1
8
DFN8
MN SUFFIX
CASE 506AA
5I
D
G
14
2X
D
G
14
(Note: Microdot may be in either location)
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