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参数资料
| 型号： | IDT7134LA20JG8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 32KBIT 20NS 52PLCC |
| 标准包装： | 400 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 32K (4K x 8) |
| 速度： | 20ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 52-LCC（J 形引线） |
| 供应商设备封装： | 52-PLCC（19x19） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7134LA20JG8 |
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 2, CE Controlled Timing (1,4)
t WC
ADDRESS
t AW
CE
R/ W
t AS (5)
t EW (2)
t DW
t WR (3)
t DH
DATA IN
2720 drw 12
NOTES:
1. R/ W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of a CE =V IL and R/ W = V IL .
3. t WR is measured from the earlier of CE or R/ W going HIGH to the end-of-write cycle.
4. If the CE LOW transition occurs simultaneously with or after the R/ W LOW transition, the outputs remain in the High-impedance state.
5. Timing depends on which enable signal ( CE or R/ W ) is asserted last.
Functional Description
The IDT7134 provides two ports with separate control, address,
and I/O pins that permit independent access for reads or writes to any
location in memory. These devices have an automatic power down
Truth Table I – Read/Write Control
Left or Right Port (1)
R/ W CE OE D 0-7 Function
feature controlled by CE . The CE controls on-chip power down circuitry
that permits the respective port to go into standby mode when not
selected ( CE HIGH). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output Enable
control ( OE ). In the read mode, the port’s OE turns on the output drivers
when set LOW. Non-contention READ/WRITE conditions are illustrated
inTruth Table I.
X
X
L
H
X
H
H
L
L
X
X
X
X
L
H
Z
Z
DATA IN
DATA OUT
Z
Port Deselected and in Power-Down
Mode, I SB2 or I SB4
CE R = CE L = H, Power Down
Mode I SB1 or I SB3
Data on port written into memory
Data in memory output on port
High impedance outputs
10
NOTE:
1. A 0L - A 11L ≠ A 0R - A 11R
"H" = V IH , "L" = V IL , "X" = Don’t Care, and "Z" = High Impedance
2720 tbl 11
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