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参数资料
| 型号： | IDT7134LA20JG8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 32KBIT 20NS 52PLCC |
| 标准包装： | 400 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 32K (4K x 8) |
| 速度： | 20ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 52-LCC（J 形引线） |
| 供应商设备封装： | 52-PLCC（19x19） |
| 包装： | 带卷 (TR) |
| 其它名称： | 7134LA20JG8 |
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read (1,2,3)
t WC
ADDR "A"
MATCH
R/ W "A"
DATA IN "A"
ADDR "B"
DATA OUT "B"
(1)
t WP
t DW
VALID
MATCH
t WDD
t AW
VALID
NOTES:
t DDD
2720 drw 10
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CE L = CE R = V IL. OE "B" = V IL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
Timing Waveform of Write Cycle No. 1, R/ W Controlled Timing (1,5,8)
t WC
ADDRESS
OE
t AS (6)
CE
R/ W
t AW
t WP (2)
t WR (3)
t HZ (7)
t LZ
DATA OUT
(7)
t WZ (7)
(4)
t DW
t OW
t DH
t HZ (7)
(4)
DATA IN
NOTES:
2720 drw 11
1. R/ W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of a CE =V IL and R/ W = V IL .
3. t WR is measured from the earlier of CE or R/ W going to V IH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE = V IL transition occurs simultaneously with or after the R/ W = V IL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal ( CE or R/ W ) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE = V IL during a R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off data to be placed on the bus
for the required t DW . If OE = V IH during an R /W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP .
9
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