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参数资料
| 型号： | DSPIC33FJ256MC710-I/PT |
| 厂商： | Microchip Technology |
| 文件页数： | 17/90页 |
| 文件大小： | 0K |
| 描述： | IC DSPIC MCU/DSP 256K 100TQFP |
| 产品培训模块： | dsPIC33F DMAC Introduction to dsPIC33F Architecture Part 1 Asynchronous Stimulus Introduction to dsPIC33F Architecture Part 2 |
| 特色产品： | PIC24FJ/33FJ MCUs & dsPIC? DSCs |
| 标准包装： | 119 |
| 系列： | dsPIC™ 33F |
| 核心处理器： | dsPIC |
| 芯体尺寸： | 16-位 |
| 速度： | 40 MIP |
| 连通性： | CAN，I²C，IrDA，LIN，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，DMA，电机控制 PWM，QEI，POR，PWM，WDT |
| 输入/输出数： | 85 |
| 程序存储器容量： | 256KB（256K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 30K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 24x10b/12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-TQFP |
| 包装： | 托盘 |
| 产品目录页面： | 654 (CN2011-ZH PDF) |
| 配用： | 876-1001-ND - DSPIC33 BREAKOUT BOARD AC164333-ND - MODULE SKT FOR PM3 100QFP MA330013-ND - MODULE PLUG-IN DSPIC33 100TQFP DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2 DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32 |
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dsPIC33F
DS70155C-page 22
Preliminary
2005 Microchip Technology Inc.
7.0
DEVICE POWER MANAGEMENT
Power
management
services
provided
by
the
dsPIC33F devices include:
Real-Time Clock Source Switching
Power-Saving Modes
7.1
Real-Time Clock Source Switching
Configuration bits determine the clock source upon
Power-on Reset (POR) and Brown-out Reset (BOR).
Thereafter, the clock source can be changed between
permissible clock sources. The OSCCON register
controls the clock switching and reflects system clock
related status bits. To reduce power consumption, the
user can switch to a slower clock source.
7.2
Power-Saving Modes
The dsPIC33F devices have two reduced power
modes that can be entered through execution of the
PWRSAV
instruction.
Sleep Mode: The CPU, system clock source and
any peripherals that operate on the system clock
source are disabled. This is the lowest power
mode of the device.
Idle Mode: The CPU is disabled but the system
clock source continues to operate. Peripherals
continue to operate but can optionally be disabled.
Doze Mode: The CPU clock is temporarily slowed
down relative to the peripheral clock by a
user-selectable factor.
These modes provide an effective way to reduce power
consumption during periods when the CPU is not in use.
7.2.1
SLEEP MODE
When the device enters Sleep mode:
System clock source is shut down. If an on-chip
oscillator is used, it is turned off.
Device current consumption is at minimum
provided that no I/O pin is sourcing current.
Fail-Safe Clock Monitor (FSCM) does not operate
during Sleep mode because the system clock
source is disabled.
LPRC clock continues to run in Sleep mode if the
WDT is enabled.
BOR circuit, if enabled, remains operative during
Sleep mode
WDT, if enabled, is automatically cleared prior to
entering Sleep mode.
Some peripherals may continue to operate in
Sleep mode. These peripherals include I/O pins
that detect a change in the input signal, or
peripherals that use an external clock input. Any
peripheral that is operating on the system clock
source is disabled in Sleep mode.
The processor exits (wakes up) from Sleep on one of
these events:
Any interrupt source that is individually enabled
Any form of device Reset
A WDT time-out
7.2.2
IDLE MODE
When the device enters Idle mode:
CPU stops executing instructions
WDT is automatically cleared
System clock source remains active
Peripheral modules, by default, continue to
operate normally from the system clock source
Peripherals, optionally, can be shut down in Idle
mode using their ‘stop-in-idle’ control bit.
If the WDT or FSCM is enabled, the LPRC also
remains active
The processor wakes from Idle mode on these events:
Any interrupt that is individually enabled
Any source of device Reset
A WDT time-out
Upon wake-up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately
starting with the instruction following the PWRSAV
instruction, or the first instruction in the Interrupt
Service Routine (ISR).
7.2.3
DOZE MODE
The Doze mode provides the user software the ability
to temporarily reduce the processor instruction cycle
frequency relative to the peripheral frequency. Clock
frequency ratios of 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64
and 1:128 are supported.
For example, suppose the device is operating at
20 MIPS and the CAN module has been configured for
500 kbps bit rate based on this device operating speed.
If the device is now placed in Doze mode with a clock
frequency ratio of 1:4, the CAN module will continue to
communicate at the required bit rate of 500 kbps, but
the CPU now starts executing instructions at a
frequency of 5 MIPS.
This feature further reduces the power consumption
during periods where relatively less CPU activity is
required.
When the device is operating in Doze mode, the
hardware
ensures
that
there
is
no
loss
of
synchronization between peripheral events and SFR
accesses by the CPU.
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