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参数资料
| 型号： | DSPIC33FJ256MC710-I/PT |
| 厂商： | Microchip Technology |
| 文件页数： | 2/90页 |
| 文件大小： | 0K |
| 描述： | IC DSPIC MCU/DSP 256K 100TQFP |
| 产品培训模块： | dsPIC33F DMAC Introduction to dsPIC33F Architecture Part 1 Asynchronous Stimulus Introduction to dsPIC33F Architecture Part 2 |
| 特色产品： | PIC24FJ/33FJ MCUs & dsPIC? DSCs |
| 标准包装： | 119 |
| 系列： | dsPIC™ 33F |
| 核心处理器： | dsPIC |
| 芯体尺寸： | 16-位 |
| 速度： | 40 MIP |
| 连通性： | CAN，I²C，IrDA，LIN，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，DMA，电机控制 PWM，QEI，POR，PWM，WDT |
| 输入/输出数： | 85 |
| 程序存储器容量： | 256KB（256K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 30K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 24x10b/12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-TQFP |
| 包装： | 托盘 |
| 产品目录页面： | 654 (CN2011-ZH PDF) |
| 配用： | 876-1001-ND - DSPIC33 BREAKOUT BOARD AC164333-ND - MODULE SKT FOR PM3 100QFP MA330013-ND - MODULE PLUG-IN DSPIC33 100TQFP DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2 DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32 |
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dsPIC33F
DS70155C-page 8
Preliminary
2005 Microchip Technology Inc.
3.1.2
ADDRESSING MODES OVERVIEW
Overhead-free circular buffers (modulo addressing) are
supported in both X and Y address spaces. The
modulo addressing removes the software boundary
checking overhead for DSP algorithms. Furthermore,
the X AGU circular addressing can be used with any of
the MCU class of instructions. The X AGU also
supports bit-reversed addressing to greatly simplify
input or output data reordering for radix-2 FFT
algorithms.
The CPU supports Inherent (no operand), Relative,
Literal, Memory Direct, Register Direct and Register
Indirect
Addressing
modes.
Each
instruction
is
associated with a predefined addressing mode group
depending upon its functional requirements. As many
as 6 addressing modes are supported for each
instruction.
For most instructions, the dsPIC33F is capable of
executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
3.1.3
DSP ENGINE OVERVIEW
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier,
a
40-bit
ALU,
two
40-bit
saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value,
up to 16 bits right or left, in a single cycle. The DSP
instructions
operate
seamlessly
with
all
other
instructions and have been designed for optimal real-
time performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the
result
in
the
same
cycle.
This
instruction
functionality requires that the RAM memory data space
be split for these instructions and linear for all others.
Data space partitioning is achieved in a transparent
and flexible manner through dedicating certain working
registers to each address space.
3.1.4
SPECIAL MCU FEATURES
The dsPIC33F features a 17-bit by 17-bit, single-cycle
multiplier that is shared by both the MCU ALU and DSP
engine. The multiplier can perform signed, unsigned
and mixed-sign multiplication. Using a 17-bit by 17-bit
multiplier for 16-bit by 16-bit multiplication not only
allows you to perform mixed-sign multiplication, it also
achieves accurate results for special operations such
as (-1.0) x (-1.0).
The dsPIC33F supports 16/16 and 32/16 divide
operations, both fractional and integer. All divide
instructions are iterative operations. They must be
executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those 19
cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
3.1.5
INTERRUPT OVERVIEW
The dsPIC33F has a vectored exception scheme with
up to 5 sources of non-maskable traps and 67 interrupt
sources. Each interrupt source can be assigned to one
of seven priority levels.
3.1.6
FEATURES TO ENHANCE
COMPILER EFFICIENCY
In addition to extensive DSP capability, the CPU
architecture possesses several features that lead to a
more efficient (code size and speed) C compiler.
1.
For most instructions, three-parameter instruc-
tions can be supported, allowing A + B = C
operations to be executed in a single cycle.
2.
Instruction addressing modes are extremely
flexible to meet compiler needs.
3.
The working register array consists of 16 x 16-bit
registers, each of which can act as data,
address or offset registers. One working register
(W15) operates as the software Stack Pointer
for interrupts and calls.
4.
Linear indirect access of all data space is
possible, plus the memory direct address range
is up to 8 Kbytes. This capability, together with
the addition of 16-bit direct address MOV-based
instructions, has provided a contiguous linear
addressing space.
5.
Linear indirect access of 32K word (64 Kbyte)
pages within program space is possible, using
any working register via new table read and
write instructions.
6.
Part of data space can be mapped into program
space, allowing constant data to be accessed as
if it were in data space.
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