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参数资料
| 型号： | DS17485SN-5+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 19/31页 |
| 文件大小： | 0K |
| 描述： | IC RTC 5V 4K NV RAM 24-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 31 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，夏令时，闰年，NVSRAM，方波输出 |
| 存储容量： | 4KB |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电压 - 电源，电池： | 2.5 V ~ 3.7 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 管件 |
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DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Bit 7: Auxiliary Battery Enable (ABE). When written to
logic 1, this bit enables the VBAUX pin for extended
functions.
Bit 6: Enable 32.768kHz Output (E32k). When written
to logic 1, this bit enables the 32.768kHz oscillator fre-
quency to be output on the SQW pin. E32k is set to 1
when VCC is powered up.
Bit 5: Crystal Select (CS). When CS is set to 0, the
oscillator is configured for operation with a crystal that
has a 6pF specified load capacitance. When CS = 1,
the oscillator is configured for a 12.5pF crystal. CS is
disabled in the DS17x87 module and should be set to
CS = 0.
Bit 4: RAM Clear Enable (RCE). When set to 1, this bit
enables a low level on RCLR to clear all 114 bytes of
user RAM. When RCE = 0, RCLR and the RAM clear
function are disabled.
Bit 3: PAB Reset Select (PRS). When set to 0, the
PWR pin is set high impedance when the DS17x85
goes into power fail. When set to 1, the PWR pin
remains active upon entering power fail.
Bit 2: RAM Clear Interrupt Enable (RIE). When RIE is
set to 1, the IRQ pin is driven low when a RAM clear
function is completed.
Bit 1: Wake-Up Alarm Interrupt Enable (WIE). When
VCC voltage is absent and WIE is set to 1, the PWR pin
is driven active low when a wake-up condition occurs,
causing the WF bit to be set to 1. When VCC is then
applied, the IRQ pin is also driven low. If WIE is set
while system power is applied, both IRQ and PWR are
driven low in response to WF being set to 1. When WIE
is cleared to 0, the WF bit has no effect on the PWR or
IRQ pins.
Bit 0: Kickstart Interrupt Enable (KSE). When VCC
voltage is absent and KSE is set to 1, the PWR pin is
driven active low when a kickstart condition occurs (KS
pulsed low), causing the KF bit to be set to 1. When
VCC is then applied, the IRQ pin is also driven low. If
KSE is set to 1 while system power is applied, both IRQ
and PWR are driven low in response to KF being set to
1. When KSE is cleared to 0, the KF bit has no effect on
the PWR or IRQ pins.
Real-Time Clocks
26
____________________________________________________________________
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ABE
E32k
CS
RCE
PRS
RIE
WIE
KSE
Extended Control Register (4Bh)
MSB
LSB
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