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| 型号： | 500DCAE-ACF |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 2/8页 |
| 文件大小： | 0K |
| 描述： | OSC PROG LVDS 3.3V 150PPM OE SMD |
| 特色产品： | Si500 Low Jitter Silicon Oscillators |
| 标准包装： | 100 |
| 系列： | Si500D，低抖动 |
| 类型： | 由 Digi-Key 编程（请在网站订购单中输入您需要的频率） |
| 可用频率范围： | 0.9MHz ~ 200MHz |
| 功能： | 三态（输出启用） |
| 输出： | LVDS |
| 电源电压： | 3.3V |
| 频率稳定性： | ±150ppm |
| 工作温度： | 0°C ~ 70°C |
| 电流 - 电源（最大）： | 16.5mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-SMD，无引线（DFN，LCC） |
| 高度： | 0.035"（0.90mm） |
| 尺寸/尺寸： | 0.157" L x 0.126" W（4.00mm x 3.20mm） |
| 包装： | 管件 |
| 电流 - 电源（禁用）（最大）： | 10.7mA |
| 产品目录页面： | 1699 (CN2011-ZH PDF) |
| 其它名称： | 500DCAE-ACFR 500DCAE-ACFR-ND |
Si500D
Parameters
Supply Current
Output Symmetry
Rise and Fall Times (20/80%) 3
LVPECL Output Option
(DC coupling, 50 ? to V DD – 2.0 V) 3
Low Power LVPECL Output Option
(AC coupling, 100 ? Differential
Load) 3
LVDS Output Option (2.5/3.3 V)
(R TERM = 100 ? diff) 3
LVDS Output Option (1.8 V)
(R TERM = 100 ? diff) 3
HCSL Output Option 3
CMOS Output Voltage 3
SSTL-1.8 Output Voltage 4
SSTL-2.5 Output Voltage 4
SSTL-3.3 Output Voltage 5
Powerup Time
OE Deassertion to Clk Stop
Return from Output Driver Stopped
Mode
Return From Tri-State Time
Condition
LVPECL
Low Power LVPECL
LVDS
HCSL
Differential CMOS(3.3 V option,
10 pF on each output, 200 MHz)
Differential CMOS(3.3 V option,
1 pFon each output, 40 MHz)
Differential SSTL-3.3
Differential SSTL-2.5
Differential SSTL-1.8
Tri-State
Powerdown
V DIFF = 0
LVPECL/LVDS
HCSL/Differential SSTL
Differential CMOS, 15 pF, >80 MHz
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
DC termination per pad
V OH , sourcing 9 mA
V OL , sinking 9 mA
V OH
V OL
V OH
V OL
V OH
V OL
From time V DD crosses min spec
supply
Min
—
—
—
—
—
—
—
—
—
—
—
46 – 13 ns/T CLK
—
—
—
V DD – 1.5
.720
—
.68
1.15
0.25
0.85
0.25
0.35
0.65
45
V DD – 0.6
—
V TT + 0.375
—
V TT + 0.48
—
V TT + 0.48
—
—
—
—
—
Typ
34.0
19.3
14.9
25.3
33
16
24.5
24.3
22.2
9.7
1.0
—
—
—
1.1
—
—
N/A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
36.0
22.2
16.5
29.3
36
—
27.7
26.7
25
10.7
1.9
54 + 13 ns/T CLK
460
800
1.6
V DD – 1.34
.880
—
.95
1.26
0.45
0.96
0.45
0.425
0.82
55
—
0.6
—
V TT – 0.375
—
V TT – 0.48
—
V TT – 0.48
2
250 + 3 x T CLK
250 + 3 x T CLK
12 + 3 x T CLK
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
%
ps
ps
ns
V
V PK
V
V PK
V
V PK
V
V PK
V
V PK
?
V
V
V
V
V
ms
ns
ns
μs
Notes:
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4. V TT = .5 x V DD .
5. V TT = .45 x V DD .
2
Rev. 1.1
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