- 您现在的位置：买卖IC网 > PDF目录3962 > MPC8545EVUANJ (Freescale Semiconductor)IC MPU PWRQUICC III 783-FCCBGA PDF资料下载
参数资料
| 型号： | MPC8545EVUANJ |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 6/151页 |
| 文件大小： | 0K |
| 描述： | IC MPU PWRQUICC III 783-FCCBGA |
| 标准包装： | 1 |
| 系列： | MPC85xx |
| 处理器类型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 800MHz |
| 电压： | 1.1V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 783-BBGA，FCBGA |
| 供应商设备封装： | 783-FCPBGA（29x29） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
103
Package Description
SENSEVSS
M16
—
13
Analog Signals
MVREF
A18
I
Reference
voltage signal
for DDR
MVREF
—
SD_IMP_CAL_RX
L28
I
200
to
GND
—
SD_IMP_CAL_TX
AB26
I
100
to
GND
—
SD_PLL_TPA
U26
O
—
24
Notes:
1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
local bus controller section, and is not mentioned in the DMA section even though the pin also functions as DMA_REQ2.
2. Recommend a weak pull-up resistor (2–10 k
) be placed on this pin to OV
DD.
3. A valid clock must be provided at POR if TSEC4_TXD[2] is set = 1.
4. This pin is an open drain signal.
5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
pull-down resistor. However, if
the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net
at reset, then a pullup or active driver is needed.
6. Treat these pins as no connects (NC) unless using debug address functionality.
7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k
pull-up or pull-down
resistors. See Section 20.2, “CCB/SYSCLK PLL Ratio.”
8. The value of LALE, LGPL2, and LBCTL at reset set the e500 core clock to CCB clock PLL ratio. These pins require 4.7-k
pull-up or pull-down resistors. See the Section 20.3, “e500 Core PLL Ratio.”
9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin therefore is described as an I/O for boundary scan.
10.This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI
operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit
PCI device. See the PCI Specification.
11.This output is actively driven during reset rather than being three-stated during reset.
12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13.These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking
and regulation.
14.Internal thermally sensitive resistor.
15.No connections must be made to these pins if they are not used.
16.These pins are not connected for any use.
17.PCI specifications recommend that a weak pull-up resistor (2–10 k
) be placed on the higher order pins to OV
DD when using
64-bit buffer mode (pins PCI_AD[63:32] and PCI1_C_BE[7:4]).
19.If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state
during reset.
20.This pin is only an output in FIFO mode when used as Rx flow control.
24.Do not connect.
Table 71. MPC8548E Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
相关PDF资料 |
PDF描述 |
|---|---|
| IDT70V658S12DRI | IC SRAM 2MBIT 12NS 208QFP |
| MPC8547EVUAQG | IC MPU PWRQUICC III 783-FCCBGA |
| IDT70V3589S133DRI | IC SRAM 2MBIT 133MHZ 208QFP |
| MPC8547EVUATG | IC MPU PWRQUICC III 783-FCCBGA |
| IDT70V3399S133PRFI | IC SRAM 2MBIT 133MHZ 128TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADA4004-2ARZ-RL | 功能描述:IC OPAMP GP 12MHZ DUAL 8SOIC RoHS:是 类别:集成电路 (IC) >> Linear - Amplifiers - Instrumentation 系列:iPolar® 标准包装:1 系列:- 放大器类型:通用 电路数:4 输出类型:满摆幅 转换速率:0.028 V/µs 增益带宽积:105kHz -3db带宽:- 电流 - 输入偏压:3nA 电压 - 输入偏移:100µV 电流 - 电源:3.3µA 电流 - 输出 / 通道:12mA 电压 - 电源，单路/双路(±):2.7 V ~ 12 V，±1.35 V ~ 6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:14-TSSOP 包装:剪切带 (CT) 其它名称:OP481GRUZ-REELCT |
| ADA4004-4 | 制造商:AD 制造商全称:Analog Devices 功能描述:1.8 nV/☆Hz, 36 V Precision Quad Amplifier |
| ADA4004-4_07 | 制造商:AD 制造商全称:Analog Devices 功能描述:1.8 nV/√Hz, 36 V Precision Quad Amplifier |
| ADA4004-4ACPZ-R2 | 功能描述:IC OPAMP GP 12MHZ QUAD 16LFCSP RoHS:是 类别:集成电路 (IC) >> Linear - Amplifiers - Instrumentation 系列:iPolar® 标准包装:2,500 系列:Excalibur™ 放大器类型:J-FET 电路数:1 输出类型:- 转换速率:45 V/µs 增益带宽积:10MHz -3db带宽:- 电流 - 输入偏压:20pA 电压 - 输入偏移:490µV 电流 - 电源:1.7mA 电流 - 输出 / 通道:48mA 电压 - 电源，单路/双路(±):4.5 V ~ 38 V，±2.25 V ~ 19 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:带卷 (TR) |
| ADA4004-4ACPZ-R7 | 功能描述:IC OPAMP GP 12MHZ QUAD 16LFCSP RoHS:是 类别:集成电路 (IC) >> Linear - Amplifiers - Instrumentation 系列:iPolar® 产品培训模块:Differential Circuit Design Techniques for Communication Applications 标准包装:1 系列:- 放大器类型:RF/IF 差分 电路数:1 输出类型:差分 转换速率:9800 V/µs 增益带宽积:- -3db带宽:2.9GHz 电流 - 输入偏压:3µA 电压 - 输入偏移:- 电流 - 电源:40mA 电流 - 输出 / 通道:- 电压 - 电源，单路/双路(±):3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VQFN 裸露焊盘，CSP 供应商设备封装:16-LFCSP-VQ 包装:剪切带 (CT) 产品目录页面:551 (CN2011-ZH PDF) 其它名称:ADL5561ACPZ-R7CT |
发布紧急采购，3分钟左右您将得到回复。