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参数资料
| 型号： | IDT71342LA35PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 8/14页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 32KBIT 35NS 64TQFP |
| 标准包装： | 750 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 32K (4K x 8) |
| 速度： | 35ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 71342LA35PF8 |
IDT71342SA/LA
High-Speed 4K x 8 Dual-Port Static RAM with Semaphore
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage (5)
Industrial and Commercial Temperature Ranges
71342X20
Com'l Only
71342X25
Com'l & Ind
71342X35
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
Write Cycle Time
20
____
25
____
35
____
ns
t EW
Chip Enable to End-of-Write
(3)
15
____
20
____
30
____
ns
t AW
t AS
t WP
t WR
t DW
t HZ
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time (1,2)
15
0
15
0
15
____
____
____
____
____
____
15
20
0
20
0
15
____
____
____
____
____
____
15
30
0
25
0
20
____
____
____
____
____
____
20
ns
ns
ns
ns
ns
ns
t DH
Data Hold Time
(4)
0
____
0
____
3
____
ns
Write Enable to Output in High-Z
t WZ
(1,2)
____
15
____
15
____
20
ns
t OW
t SWR
t SPS
Output Active from End-of-Write
SEM Flag Write to Read Time
SEM Flag Contention Window
(1,2,4)
3
10
10
____
____
____
3
10
10
____
____
____
3
10
10
____
____
____
ns
ns
ns
2721 tbl 10a
71342X45
Com'l Only
71342X55
Com'l Only
71342X70
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t WC
Write Cycle Time
45
____
55
____
70
____
ns
t EW
Chip Enable to End-of-Write
(3)
40
____
50
____
60
____
ns
t AW
t AS
t WP
t WR
t DW
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
40
0
40
0
20
____
____
____
____
____
50
0
50
0
25
____
____
____
____
____
60
0
60
0
30
____
____
____
____
____
ns
ns
ns
ns
ns
t HZ
Output High-Z Time
(1,2)
____
20
____
25
____
30
ns
t DH
Data Hold Time
(4)
3
____
3
____
3
____
ns
Write Enable to Output in High-Z
t WZ
(1,2)
____
20
____
25
____
30
ns
t OW
t SWR
t SPS
Output Active from End-of-Write
SEM Flag Write to Read Time
SEM Flag Contention Window
(1,2,4)
3
10
10
____
____
____
3
10
10
____
____
____
3
10
10
____
____
____
ns
ns
ns
NOTES:
2721 tbl 10b
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. To access SRAM, CE = V IL and SEM = V IH . To access semaphore, CE = V IH and SEM = V IL. Either condition must be valid for the entire t EW time.
4. The specification for t DH must be met by the device supplying write data to the SRAM under all operating conditions. Although t DH and t OW values will vary over voltage and
temperature, the actual t DH will always be smaller than the actual t OW .
5. 'X' in part number indicates power rating (SA or LA).
8
6.42
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