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参数资料
| 型号： | PIC24FJ16GA002-I/SS |
| 厂商： | Microchip Technology |
| 文件页数： | 24/52页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 16K 28-SSOP |
| 产品培训模块： | Graphics LCD System and PIC24 Interface Asynchronous Stimulus |
| 特色产品： | PIC24FJ/33FJ MCUs & dsPIC? DSCs |
| 标准包装： | 47 |
| 系列： | PIC® 24F |
| 核心处理器： | PIC |
| 芯体尺寸： | 16-位 |
| 速度： | 32MHz |
| 连通性： | I²C，PMP，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，LVD，POR，PWM，WDT |
| 输入/输出数： | 21 |
| 程序存储器容量： | 16KB（5.5K x 24） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 4K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 数据转换器： | A/D 10x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 包装： | 管件 |
| 产品目录页面： | 647 (CN2011-ZH PDF) |
| 配用： | DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU AC162088-ND - HEADER MPLAB ICD2 24FJ64GA004 28 AC164338-ND - MOD SKT PIC24F/DSPIC33F 28SOIC DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2 |
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PIC24FJXXXGA0XX
DS39768D-page 30
2008 Microchip Technology Inc.
4.5.2
PROGRAMMING VERIFICATION
After code memory is programmed, the contents of
memory can be verified to ensure that programming
was successful. Verification requires code memory to
be read back and compared against the copy held in
the programmer’s buffer.
The READP command can be used to read back all of
the programmed code memory.
Alternatively, you can have the programmer perform
the verification after the entire device is programmed
using a checksum computation.
4.6
Configuration Bits Programming
4.6.1
OVERVIEW
The PIC24FJXXXGA0XX family has Configuration bits
stored in the last two locations of implemented program
memory (see Table 2-2 for locations). These bits can
be set or cleared to select various device configura-
tions. There are three types of Configuration bits:
system operation bits, code-protect bits and unit ID bits.
The system operation bits determine the power-on
settings for system level components, such as
oscillator and Watchdog Timer. The code-protect bits
prevent program memory from being read and written.
The register descriptions for the CW1 and CW2
Configuration registers are shown in Table 4-2.
TABLE 4-2:
PIC24FJXXXGA0XX FAMILY CONFIGURATION BITS DESCRIPTION
Bit Field
Register
Description
I2C1SEL(1)
CW2<2>
I2C1 Pin Mapping bit
1
= Default location for SCL1/SDA1 pins
0
= Alternate location for SCL1/SDA1 pins
DEBUG
CW1<11>
Background Debug Enable bit
1
= Device will reset in User mode
0
= Device will reset in Debug mode
FCKSM1:FCKSM0
CW2<7:6>
Clock Switching Mode bits
1x
= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01
= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00
= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
FNOSC2:FNOSC0
CW2<10:8>
Initial Oscillator Source Selection bits
111
= Internal Fast RC (FRCDIV) oscillator with postscaler
110
= Reserved
101
= Low-Power RC (LPRC) oscillator
100
= Secondary (SOSC) oscillator
011
= Primary (XTPLL, HSPLL, ECPLL) oscillator with PLL
010
= Primary (XT, HS, EC) oscillator
001
= Internal Fast RC (FRCPLL) oscillator with postscaler and PLL
000
= Fast RC (FRC) oscillator
FWDTEN
CW1<7>
Watchdog Timer Enable bit
1
= Watchdog Timer always enabled (LPRC oscillator cannot be disabled;
clearing the SWDTEN bit in the RCON register will have no effect)
0
= Watchdog Timer enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register)
GCP
CW1<13>
General Segment Code-Protect bit
1
= User program memory is not code-protected
0
= User program memory is code-protected
GWRP
CW1<12>
General Segment Write-Protect bit
1
= User program memory is not write-protected
0
= User program memory is write-protected
ICS
CW1<8>
ICD Communication Channel Select bit
1
= Communicate on PGC2/EMUC2 and PGD2/EMUD2
0
= Communicate on PGC1/EMUC1 and PGD1/EMUD1
Note 1:
Available on 28 and 44-pin packages only.
2:
Available only on 28 and 44-pin devices with a silicon revision of 3042h or higher.
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