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参数资料
| 型号： | PIC24FJ16GA002-I/SS |
| 厂商： | Microchip Technology |
| 文件页数： | 26/52页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 16K 28-SSOP |
| 产品培训模块： | Graphics LCD System and PIC24 Interface Asynchronous Stimulus |
| 特色产品： | PIC24FJ/33FJ MCUs & dsPIC? DSCs |
| 标准包装： | 47 |
| 系列： | PIC® 24F |
| 核心处理器： | PIC |
| 芯体尺寸： | 16-位 |
| 速度： | 32MHz |
| 连通性： | I²C，PMP，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，LVD，POR，PWM，WDT |
| 输入/输出数： | 21 |
| 程序存储器容量： | 16KB（5.5K x 24） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 4K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 数据转换器： | A/D 10x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 包装： | 管件 |
| 产品目录页面： | 647 (CN2011-ZH PDF) |
| 配用： | DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU AC162088-ND - HEADER MPLAB ICD2 24FJ64GA004 28 AC164338-ND - MOD SKT PIC24F/DSPIC33F 28SOIC DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2 |
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PIC24FJXXXGA0XX
DS39768D-page 32
2008 Microchip Technology Inc.
4.6.2
PROGRAMMING METHODOLOGY
Configuration bits may be programmed a single byte at
a time using the PROGW command. This command
specifies the configuration data and Configuration
register
address.
When
Configuration
bits
are
programmed, any unimplemented or reserved bits
must be programmed with a ‘1’.
Two PROGW commands are required to program the
Configuration bits. A flowchart for Configuration bit
programming is shown in Figure 4-5.
4.6.3
PROGRAMMING VERIFICATION
After the Configuration bits are programmed, the
contents of memory should be verified to ensure that
the programming was successful. Verification requires
the Configuration bits to be read back and compared
against the copy held in the programmer’s buffer. The
READP command reads back the programmed
Configuration bits and verifies that the programming
was successful.
4.6.4
CODE-PROTECT
CONFIGURATION BITS
CW1 Configuration register controls code protection for
the PIC24FJXXXGA0XX family. Two forms of code pro-
tection are provided. One form prevents code memory
from being written (write protection) and the other
prevents code memory from being read (read protection).
GWRP (CW1<12>) controls write protection and GCP
(CW1<13>) controls read protection. Protection is
enabled when the respective bit is ‘0’.
Erasing sets GWRP and GCP to ‘1’, which allows the
device to be programmed.
When write protection is enabled (GWRP = 0), any
programming operation to code memory will fail.
When read protection is enabled (GCP = 0), any read
from code memory will cause a 0h to be read, regard-
less of the actual contents of code memory. Since the
programming
executive
always
verifies
what
it
programs, attempting to program code memory with
read protection enabled also will result in failure.
It is imperative that both GWRP and GCP are ‘1’ while
the device is being programmed and verified. Only after
the device is programmed and verified should either
GWRP or GCP be programmed to ‘0’ (see Section 4.6
Note:
If the General Segment Code-Protect bit
(GCP) is programmed to ‘0’, code memory
is code-protected and can not be read.
Code memory must be verified before
enabling read protection. See Section 4.6.4
more
information
about
code-protect
Configuration bits.
Note:
Bulk Erasing in ICSP mode is the only way
to reprogram code-protect bits from an ON
state (‘0’) to an Off state (‘1’).
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