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参数资料
| 型号： | MAX6698EE38+ |
| 厂商： | Maxim Integrated |
| 文件页数： | 3/24页 |
| 文件大小： | 321K |
| 描述： | IC TEMP MONITOR I2C 7CH 16QSOP |
| 产品培训模块： | Obsolescence Mitigation Program |
| 标准包装： | 100 |
| 功能： | 温度监控系统（传感器） |
| 传感器类型： | 内部和外部 |
| 感应温度： | -40°C ~ 125°C |
| 精确度： | ±3.5°C 本地（最大），±3°C 远程（最大） |
| 拓扑： | ADC，缓冲器，多路复用器，寄存器库 |
| 输出类型： | 2 线串行，I²C?/SMBUS? |
| 输出警报： | 是 |
| 输出风扇： | 是 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 管件 |
7-Channel Precision Remote-Diode, Thermistor,
and Local Temperature Monitor
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +5.5V, T
A
= -40癈 to +125癈, unless otherwise noted. Typical values are at V
CC
= +3.3V and T
A
= +25癈.) (Note 1)
PARAMETER
YMB L
CONDITIONS
MIN
TYP
MAX
NIT
Reference-Load Regulation
0mA < I
REF
< 2mA
0.4
%
Reference-Supply Rejection
0.5
%/V
LERT, OVERT
I
SINK
= 1mA
0.3
Output Low Voltage
V
OL
I
SINK
= 6mA
0.5
V
Output Leakage Current
1
礎
SMBus INTERFACE (SCL, SDA)
Logic-Input Low Voltage
V
IL
0.8
V
V
CC
= 3.0V
2.2
V
Logic-Input High Voltage
V
IH
V
CC
= 5.0V
2.4
V
Input Leakage Current
-1
+1
礎
Output Low Voltage
V
OL
I
SINK
= 6mA
0.3
V
Input Capacitance
C
IN
5
pF
SMBus-COMPATIBLE TIMING (Figures 3 and 4) (Note 2)
Serial Clock Frequency
f
SCL
(Note 3)
400
kHz
f
SCL
= 100kHz
4.7
Bus Free Time Between STOP
and START Condition
t
BUF
f
SCL
= 400kHz
1.6
祍
f
SCL
= 100kHz
4.7
START Condition Setup Time
f
SCL
= 400kHz
0.6
祍
90% of SCL to 90% of SDA, f
SCL
= 100kHz
0.6
Repeat START Condition Setup
Time
t
SU:STA
90% of SCL to 90% of SDA, f
SCL
= 400kHz
0.6
祍
START Condition Hold Time
t
HD:STA
10% of SDA to 90% of SCL
0.6
祍
90% of SCL to 90% of SDA, f
SCL
= 100kHz
4
STOP Condition Setup Time
t
SU:STO
90% of SCL to 90% of SDA, f
SCL
= 400kHz
0.6
祍
10% to 10%, f
SCL
= 100kHz
1.3
Clock Low Period
t
LOW
10% to 10%, f
SCL
= 400kHz
1.3
祍
Clock High Period
t
HIGH
90% to 90%
0.6
祍
f
SCL
= 100kHz
300
Data Hold Time
t
HD:DAT
f
SCL
= 400kHz (Note 4)
900
ns
f
SCL
= 100kHz
250
Data Setup Time
t
SU:DAT
f
SCL
= 400kHz
100
ns
f
SCL
= 100kHz
1
Receive SCL/SDA Rise Time
t
R
f
SCL
= 400kHz
0.3
祍
Receive SCL/SDA Fall Time
t
F
300
ns
P l Wi h f ik
r
t
SP
0
50
ns
SMBus Timeout
t
TIMEOUT
SDA low period for interface reset
25
37
45
ms
Note 1: All parameters are tested at T
A
= +25癈. Specifications over temperature are guaranteed by design.
Note 2: Timing specifications are guaranteed by design.
Note 3: The serial interface resets when SCL is low for more than t
TIMEOUT
.
Note 4: A transition must internally provide at least a hold time to bridge the undefined region (300ns max) of SCLs falling edge.
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