参数资料
型号: ADP2325ACPZ-R7
厂商: Analog Devices Inc
文件页数: 1/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 32LFCSP
标准包装: 1
PWM 型: 电流模式
输出数: 2
频率 - 最大: 1.2MHz
占空比: 90%
电源电压: 4.5 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 32-WFQFN 裸露焊盘,CSP
包装: 标准包装
其它名称: ADP2325ACPZ-R7DKR

Dual 5 A, 20 V Synchronous Step-Down
Regulator with Integrated High-Side MOSFET
Data Sheet
FEATURES
Input voltage: 4.5 V to 20 V
TYPICAL APPLICATION CIRCUIT
±1% output accuracy
Integrated 48 mΩ typical high-side MOSFET
Flexible output configuration
R TOP1
R BOT1
C C1
C SS1
R C1
C IN1
V IN
Dual output: 5 A/5 A
Parallel single output: 10 A
Programmable switching frequency: 250 kHz to 1.2 MHz
External synchronization input with programmable phase
C INT
INTVCC
MODE
SCFG
TRK2
TRK1
SW1
DL1
M1
C BST1
L1
C OUT1
V OUT1
shift or internal clock output
Selectable PWM or PFM mode operation
Adjustable current limit for small inductors
External compensation and soft start
Startup into precharged output
Supported by ADIsimPower ? design tool
C DRV
R OSC
VDRV
GND
PGOOD2
PGOOD1
SYNC
RT
ADP2325
PGND
DL2
SW2
M2
C OUT2
L2
C BST2
V OUT2
APPLICATIONS
R BOT2
R C2
V IN
Communications infrastructure
Networking and servers
R TOP2
C C2
C SS2
C IN2
V OUT = 3.3V
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
GENERAL DESCRIPTION
The ADP2325 is a full featured, dual output, step-down dc-to-dc
regulator based on a current mode architecture. The ADP2325
integrates two high-side power MOSFETs and two low-side drivers
for the external N-channel MOSFETs. The two pulse-width mod-
ulation (PWM) channels can be configured to deliver dual 5 A
outputs or a parallel-to-single 10 A output. The regulator operates
from input voltages of 4.5 V to 20 V, and the output voltage can
be as low as 0.6 V.
The switching frequency can be programmed from 250 kHz to
1.2 MHz, or it can be synchronized to an external clock to
minimize interference in multirail applications. The dual PWM
channels run 180° out of phase, thereby reducing input current
ripple as well as reducing the size of the input capacitor.
The bidirectional synchronization pin can be programmed at
a 60°, 90°, or 120° phase shift to provide for a stackable, multi-
phase power solution.
The ADP2325 can be configured to operate in pulse frequency
modulation (PFM) mode at a light load for higher efficiency or
Figure 1.
Independent enable inputs and power-good outputs provide
reliable power sequencing. To enhance system reliability, the device
includes undervoltage lockout (UVLO), overvoltage protection
(OVP), overcurrent protection, and thermal shutdown.
The ADP2325 operates over the ?40°C to +125°C junction
temperature range and is available in a 32-lead LFCSP_WQ
package.
100
V OUT = 5.0V
95
90
85
80
75
70
65
60
55
in forced PWM mode for noise sensitive applications. External
compensation and soft start provide design flexibility.
50
0
0.5
1.0
1.5 2.0 2.5 3.0 3.5
OUTPUT CURRENT (A)
4.0
4.5
5.0
Figure 2. Efficiency vs. Output Current at V IN = 12 V, f SW = 600 kHz
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ?2012 Analog Devices, Inc. All rights reserved.
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