参数资料
型号: ADP322ACPZ-115-R7
厂商: Analog Devices Inc
文件页数: 1/24页
文件大小: 0K
描述: IC REG LDO 3.3/2.8/1.8V 16LFCSP
标准包装: 1
稳压器拓扑结构: 正,固定式
输出电压: 3.3V,2.8V,1.8V
输入电压: 1.8 V ~ 5.5 V
电压 - 压降(标准): 0.11V @ 200mA,0.11V @ 200mA,-
稳压器数量: 3
电流 - 输出: 200mA(最小值)
电流 - 限制(最小): 250mA
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-WFQFN 裸露焊盘,CSP
供应商设备封装: 16-LFCSP-WQ(3x3)
包装: 标准包装
其它名称: ADP322ACPZ-115-R7DKR

Triple, 200 mA, Low Noise,
High PSRR Voltage Regulator
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUITS
Fixed (ADP322) and adjustable output (ADP323) options
Bias voltage range (VBIAS): 2.5 V to 5.5 V
LDO input voltage range (VIN1/VIN2, VIN3): 1.8 V to 5.5 V
2.5V TO VBIAS
5.5V
+
1μF
ADP322
VBIAS
Three 200 mA low dropout voltage regulators (LDOs)
16-lead, 3 mm × 3 mm LFCSP
Initial accuracy: ±1%
Stable with 1 μF ceramic output capacitors
No noise bypass capacitor required
3 independent logic controlled enables
Overcurrent and thermal protection
Key specifications
High PSRR
1.8V TO VIN1/VIN2
5.5V
1.8V TO VIN3
5.5V
+
+
1μF
EN1
EN2
1μF
EN3
OFF
OFF
OFF
ON
ON
ON
LDO 1
EN LD1
VBIAS
LDO 2
EN LD2
VBIAS
LDO 3
EN LD3
VOUT1
+
1μF
VOUT2
+
1μF
VOUT3
+
1μF
76 dB PSRR up to 1 kHz
70 dB PSRR at 10 kHz
60 dB PSRR at 100 kHz
40 dB PSRR at 1 MHz
GND
Figure 1. Typical Application Circuit for ADP322
Low output noise
29 μV rms typical output noise at V OUT = 1.2 V
55 μV rms typical output noise at V OUT = 2.8 V
2.5V TO VBIAS
5.5V
+
1μF
ADP323
VBIAS
Excellent transient response
Low dropout voltage: 110 mV at 200 mA load
85 μA typical ground current at no load, all LDOs enabled
1.8V TO VIN1/VIN2
5.5V
+
1μF
EN1
OFF
ON
LDO 1
EN LD1
FB1
VOUT1
+
1μF
100 μs fast turn-on circuit
VBIAS
Guaranteed 200 mA output current per regulator
?40°C to +125°C junction temperature
APPLICATIONS
EN2
OFF
ON
LDO 2
EN LD2
VBIAS
FB2
VOUT2
+
1μF
Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
1.8V TO VIN3
5.5V
+
1μF
EN3
OFF
ON
LDO 3
EN LD3
FB3
VOUT3
+
1μF
Portable medical devices
GND
Post dc-to-dc regulation
Figure 2. Typical Application Circuit for ADP323
GENERAL DESCRIPTION
The ADP322/ADP323 200 mA triple output LDOs combine high
PSRR, low noise, low quiescent current, and low dropout voltage
to extend the battery life of portable devices and are ideally
suited for wireless applications with demanding performance
and board space requirements.
The ADP322/ADP323 PSRR is greater than 60 dB for frequencies
as high as 100 kHz while operating with a low headroom voltage.
The ADP322/ADP323 offer much lower noise performance
than competing LDOs without the need for a noise bypass
capacitor.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The ADP322/ADP323 are available in a miniature 16-lead,
3 mm × 3 mm LFCSP package and are stable with tiny 1 μF
±30% ceramic output capacitors providing the smallest possible
board area for a wide variety of portable power needs.
The ADP322 is available in output voltage combinations ranging
from 0.8 V to 3.3 V and offers overcurrent and thermal protection
to prevent damage in adverse conditions. The APDP323
adjustable triple LDO can be configured for any output voltage
between 0.5 V and 5 V with two resistors for each output.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ?2010–2011 Analog Devices, Inc. All rights reserved.
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