参数资料
型号: ADS1252U/2K5G4
厂商: Texas Instruments
文件页数: 4/21页
文件大小: 0K
描述: IC ADC 24-BIT SER 41.7KHZ 8-SOIC
产品培训模块: Data Converter Basics
视频文件: Nuts and Bolts of the Delta-Sigma Converter
标准包装: 2,500
位数: 24
采样率(每秒): 41.7k
数据接口: 串行
转换器数目: 1
功率耗散(最大): 40mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
输入数目和类型: 1 个差分,双极
配用: 296-19906-ND - EVAL MOD FOR ADS1252
ADS1252
12
SBAS127D
www.ti.com
POWER-DOWN MODE
The normal state of SCLK is LOW; however, by holding
SCLK HIGH, the ADS1252 enters power-down mode. This is
accomplished by holding SCLK HIGH for at least 20 con-
secutive DOUT/DRDY periods (see Figure 14). After the
ADS1252 circuitry detects that SCLK is held HIGH for four
consecutive DOUT/DRDY cycles, the DOUT/DRDY pin pulses
LOW for three CLK cycles, then held HIGH, and the modu-
lator will be held in a reset state. If SCLK is held HIGH for an
additional 16 DOUT/DRDY periods, the ADS1252 enters
power-down mode and the part is released from power-down
mode on the falling edge of SCLK. It is important to note that
the DOUT/DRDY pin is held HIGH after four DOUT/DRDY
cycles, but power-down mode is not entered for an additional
16 DOUT/DRDY periods. The first DOUT/DRDY pulse after
the falling edge of SCLK occurs at t16; however, subsequent
DOUT/DRDY pulses occur normally. Valid data is not present
until the sixth DOUT/DRDY pulse.
SERIAL INTERFACE
The ADS1252 includes a simple serial interface which can be
connected to microcontrollers and digital signal processors in
a variety of ways. Communications with the ADS1252 can
commence on the first detection of the DOUT/DRDY pulse
after power up, although data is valid until the sixth conver-
sion.
It is important to note that the data from the ADS1252 is a
24-bit result transmitted MSB-first in Offset Binary Two’s
Complement format, as shown in Table III.
The data must be clocked out before the ADS1252 enters
DRDY mode to ensure reception of valid data, as described
in the DOUT/DRDY section of this data sheet.
FIGURE 11. DOUT/DRDY Partitioning.
DATA
DRDY Mode
DOUT Mode
DATA
t
4
t
2
t
3
t
1
DRDY Mode
DOUT/DRDY
TABLE III. ADS1252 Data Format (Offset Binary Two's
Complement).
DIFFERENTIAL VOLTAGE INPUT
DIGITAL OUTPUT (HEX)
+Full-Scale
7FFFFFH
Zero
000000H
–Full-Scale
800000H
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tDRDY
Conversion Cycle
384 CLK
ns
DRDY Mode
36 CLK
ns
DOUT Mode
348 CLK
ns
t1
DOR Write Time
6 CLK
ns
t2
DOUT/DRDY LOW Time
6 CLK
ns
t3
DOUT/DRDY HIGH Time (Prior to Data Out)
6 CLK
ns
t4
DOUT/DRDY HIGH Time (Prior to Data Ready)
24 CLK
ns
t5
Rising Edge of CLK to Falling Edge of DOUT/DRDY
30
ns
t6
End of DRDY Mode to Rising Edge of First SCLK
30
ns
t7
End of DRDY Mode to Data Valid (Propagation Delay)
30
ns
t8
Falling Edge of SCLK to Data Valid (Hold Time)
5
ns
t9
Falling Edge of SCLK to Next Data Out Valid (Propagation Delay)
30
ns
t10
SCLK Setup Time for Synchronization or Power Down
30
ns
t11
DOUT/DRDY Pulse for Synchronization or Power Down
3 CLK
ns
t12
Rising Edge of SCLK Until Start of Synchronization
1537 CLK
7679 CLK
ns
t13
Synchronization Time
0.5 CLK
6143.5 CLK
ns
t14
Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode
2042.5 CLK
ns
t15
Rising Edge of SCLK Until Start of Power Down
7681 CLK
ns
t16
Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode
591.5 CLK
592.5 CLK
ns
t17
Falling Edge of Last DOUT/DRDY to Start of Power Down
6143.5 CLK
ns
TABLE II. Digital Timing.
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