参数资料
型号: DSPIC33FJ16GP304T-I/PT
厂商: Microchip Technology
文件页数: 30/176页
文件大小: 0K
描述: IC DSPIC MCU/DSP 16K 44TQFP
产品培训模块: Asynchronous Stimulus
标准包装: 1,200
系列: dsPIC™ 33F
核心处理器: dsPIC
芯体尺寸: 16-位
速度: 40 MIP
连通性: I²C,IrDA,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 35
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 13x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-TQFP
包装: 带卷 (TR)
配用: DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名称: DSPIC33FJ16GP304T-I/PTTR
123
AT89C5131
4136C–USB–04/05
Bulk/Interrupt IN Transactions
in Standard Mode
Figure 61. Bulk/Interrupt IN Transactions in Standard Mode
An endpoint will be first enabled and configured before being able to send Bulk or Inter-
rupt packets.
The firmware will fill the FIFO with the data to be sent and set the TXRDY bit in the UEP-
STAX register to allow the USB controller to send the data stored in FIFO at the next IN
request concerning this endpoint. To send a Zero Length Packet, the firmware will set
the TXRDY bit without writing any data into the endpoint FIFO.
Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK
handshake for each IN requests.
To cancel the sending of this packet, the firmware has to reset the TXRDY bit. The
packet stored in the endpoint FIFO is then cleared and a new packet can be written and
sent.
When the IN packet has been sent and acknowledged by the Host, the TXCMPL bit in
the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if
enabled. The firmware will clear the TXCMPL bit before filling the endpoint FIFO with
new data.
The firmware will never write more bytes than supported by the endpoint FIFO.
All USB retry mechanisms are automatically managed by the USB controller.
IN
DATA0 (n Bytes)
ACK
HOST
UFI
C51
Endpoint FIFO Write Byte 1
IN
NAK
TXCMPL
Endpoint FIFO Write Byte 2
Endpoint FIFO Write Byte n
Set TXRDY
Clear TXCMPL
Endpoint FIFO Write Byte 1
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