参数资料
型号: ADS6242IRGZTG4
厂商: TEXAS INSTRUMENTS INC
元件分类: ADC
英文描述: 2-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC48
封装: 7 X 7 MM, GREEN, PLASTIC, QFN-48
文件页数: 1/76页
文件大小: 3497K
代理商: ADS6242IRGZTG4
1
FEATURES
APPLICATIONS
DESCRIPTION
SLAS542A – MAY 2007 – REVISED JULY 2007
www.ti.com
DUAL CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS
Pin Compatible 12-Bit Family (ADS622X -
Maximum Sample Rate: 125 MSPS
Feature Compatible Quad Channel Family
14-Bit Resolution with No Missing Codes
(ADS644X - SLAS531A and ADS642X -
Simultaneous Sample and Hold
3.5 dB Coarse Gain and up to 6 dB
Programmable Fine Gain for SFDR/SNR
Trade-Off
Base-Station IF Receivers
Serialized LVDS Outputs with Programmable
Diversity Receivers
Internal Termination Option
Medical Imaging
Supports Sine, LVCMOS, LVPECL, LVDS
Test Equipment
Clock Inputs and Amplitude down to 400 mVpp
Internal Reference with External Reference
Table 1. ADS62XX Dual Channel Family
Support
125 MSPS 105 MSPS 80 MSPS
65 MSPS
No External Decoupling Required for
ADS624X
ADS6245
ADS6244
ADS6243
ADS6242
References
14 Bit
ADS622X
3.3-V Analog and Digital Supply
ADS6225
ADS6224
ADS6223
ADS6222
12 Bit
48 QFN Package (7 mm
× 7 mm)
Table 2. Performance Summary
ADS6245
ADS6244
ADS6243
ADS6242
Fin = 10MHz (0 dB gain)
87
91
92
93
SFDR, dBc
Fin = 170MHz (3.5 dB gain)
79
83
84
Fin = 10MHz (0 dB gain)
73.4
74.2
74.3
SINAD, dBFS
Fin = 170MHz (3.5 dB gain)
68.3
69.3
69.4
70
Power, per channel, mW
500
405
350
315
ADS6245/ADS6244/ADS6243/ADS6242 (ADS624X) is a family of high performance 14-bit 125/105/80/65 MSPS
dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a
compact 48-pin QFN package (7 mm
× 7mm) that allows for high system integration density. The device includes
3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In
addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it
possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing
receiver design. The ADS624X also includes the traditional 1-wire interface that can be used at lower sampling
frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit
clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and
bit clocks are also transmitted as LVDS outputs.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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