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参数资料
| 型号： | AM29LV200BB50DTE1 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory, Die Revison 1 |
| 中文描述： | 2兆位（256亩x 8-Bit/128亩x 16位），3.0伏的CMOS只，引导扇区快闪记忆体，修编模具1 |
| 文件页数： | 2/11页 |
| 文件大小： | 200K |
| 代理商： | AM29LV200BB50DTE1 |
2
Am29LV200B Known Good Die
November 18, 2003
S U P P L E M E N T
GENERAL DESCRIPTION
The Am29LV200B in Known Good Die (KGD) form is a
2 Mbit, 3.0 volt-only Flash memory. AMD defines KGD
as standard product in die form, tested for functionality
and speed. AMD KGD products have the same reliability
and quality as AMD products in packaged form.
Am29LV200B Features
The Am29LV200B is an 2 Mbit, 3 volt-only Flash
memory organized as 262,144 bytes or 131,072 words.
The word-wide data (x16) appears on DQ15–DQ0; the
byte-wide (x8) data appears on DQ7–DQ0. To elimi-
nate bus contention the device has separate chip
enable (CE#), write enable (WE#) and output enable
(OE#) controls.
The device requires only a
single 3 volt power supply
for both read and write functions. Internally generated
and regulated voltages are provided for the program
and erase operations. No V
PP
is required for program
or erase operations. The device can also be pro-
grammed in standard EPROM programmers.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard
. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase
algorithm—an internal algorithm that automati-
cally preprograms the array (if it is not already pro-
grammed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits
. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of
memory. This can be achieved in-system or via pro-
gramming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode
.
The system can also place the device into the
standby
mode
. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron injec-
tion.
Electrical Specifications
Refer to the Am29LV200B data sheet, for full electrical
specifications on the Am29LV200B in KGD form.
相关PDF资料 |
PDF描述 |
|---|---|
| AM29LV200BB50DTI1 | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory, Die Revison 1 |
| AM29LV200BB50DWC1 | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory, Die Revison 1 |
| AM29LV200BB50DWE1 | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory, Die Revison 1 |
| AM29LV200BB50DWI1 | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory, Die Revison 1 |
| AM29LV200BB-60RDFC | 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory, Die Revison 1 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM29LV200BB-90EC | 制造商:Advanced Micro Devices 功能描述:NOR Flash, 128K x 16, 48 Pin, Plastic, TSSOP |
| AM29LV200BB-90FC | 制造商:Advanced Micro Devices 功能描述:2 Mb (128K x 16) Boot Sector, Flash Memory |
| AM29LV256MH120RPGI | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 256MBIT 32MX8/16MX16 120NS 64BGA - Trays |
| AM29LV256MH123RPGI | 制造商:Advanced Micro Devices 功能描述: |
| AM29LV256MH94REI | 制造商:Spansion 功能描述:256M (32MX8/16MX16) 3V REG, MIRRORBIT, TSOP56, IND - Trays |
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