参数资料
| 型号： | ISL6323AIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 15/36页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR SYNC BUCK DL 48QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
ISL6323A
V IN
I
L
n
The North Bridge regulator samples the load current in the
same manner as the Core regulator does. The R SET resistor
MOSFET
UGATE(n)
L
DCR
V OUT
will program all the effective internal R ISEN resistors to the
same value.
DRIVER
LGATE(n)
INDUCTOR
V L (s)
C OUT
Channel-Current Balance
One important benefit of multi-phase operation is the thermal
V C (s)
advantage gained by distributing the dissipated heat over
ISL6323A INTERNAL CIRCUIT
I n
SAMPLE
R 1
C
R 2
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multi-phase converter be controlled to
carry about the same amount of current at any load level. To
achieve this, the currents through each channel must be
I SEN
+
-
V C (s)
R ISEN
ISENn-
ISENn+
VCC
sampled every switching cycle. The sampled currents, I n ,
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, I AVG , provides a measure of the total
load-current demand on the converter during each switching
RSET
R SET
C SET
FIGURE 5. INDUCTOR DCR CURRENT SENSING
CONFIGURATION
cycle. Channel-current balance is achieved by comparing
the sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented
current-balance method is illustrated in Figure 6, with error
correction for Channel 1 represented. In the figure, the cycle
L R 1 ? R
R 1 + R 2
.
------------- = -------------------- 2 - ? C
DCR
(EQ. 8)
average current, I AVG , is compared with the Channel 1
sample, I 1 , to create an error signal I ER . The filtered error
signal modifies the pulse width commanded by V COMP to
The capacitor voltage V C , is then replicated across the
effective internal sense resistor, R ISEN . This develops a
current through R ISEN which is proportional to the inductor
correct any unbalance and force I ER toward zero. The same
method for error signal correction is applied to each active
channel.
current. This current, I SEN , is continuously sensed and is
then used by the controller for load-line regulation,
channel-current balancing, and overcurrent detection and
V COMP
+
-
MODULATOR
RAMP
+
-
PWM1
TO GATE
CONTROL
LOGIC
limiting. Equation 9 shows that the proportion between the
channel current, I L , and the sensed current, I SEN , is driven
by the value of the effective sense resistance, R ISEN , and
the DCR of the inductor.
FILTER
f(s)
I ER
-
I AVG
WAVEFORM
÷ N
Σ
I 4
I 3
I SEN = I L ? ------------------
DCR
R ISEN
(EQ. 9)
+
I 2
The effective internal R ISEN resistance is important to the
current sensing process because it sets the gain of the load
line regulation loop when droop is enabled as well as the
gain of the channel-current balance loop and the overcurrent
trip level. The effective internal R ISEN resistance is user
programmable and is set through use of the RSET pin.
Placing a single resistor, R SET , from the RSET pin to the
VCC pin programs the effective internal R ISEN resistance
according to Equation 10.
I 1
NOTE: Channel 3 and 4 are optional.
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
VID Interface
The ISL6323A supports hybrid power control of AMD
processors which operate from either a 6-bit parallel VID
interface (PVI) or a serial VID interface (SVI). The VID1/SEL pin
R ISEN = ---------- ? R SET
3
400
15
(EQ. 10)
is used to command the ISL6323A into either the PVI mode or
the SVI mode. Whenever the EN pin is held LOW, both the
FN6878.1
May 12, 2010
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