参数资料
| 型号： | ISL6323AIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 27/36页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR SYNC BUCK DL 48QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6323A
P Qg_Q1 = --- ? Q G1 ? PVCC ? F SW ? N Q1 ? N PHASE
1.6
1.4
1.2
1.
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
3
2
P Qg_Q2 = Q G2 ? PVCC ? F SW ? N Q2 ? N PHASE
(EQ. 28)
I DR = ? --- ? Q G1 ? N
0.8
3
? 2
Q1
?
+ Q G2 ? N Q2 ? ? N PHASE ? F SW + I Q
(EQ. 29)
0.6
Q GATE = 100nC
In Equations 28 and 29, P Qg_Q1 is the total upper gate drive
power loss and P Qg_Q2 is the total lower gate drive power
0.4
0.2
20nC
50nC
loss; the gate charge (Q G1 and Q G2 ) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I Q is the driver total
0.0
0.0
0.1
0.2
0.3
0.4 0.5 0.6
Δ V BOOT_CAP (V)
0.7
0.8
0.9
1.0
quiescent current with no load at both drive outputs; N Q1
and N Q2 are the number of upper and lower MOSFETs per
phase, respectively; N PHASE is the number of active
FIGURE 17. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
phases. The I Q* VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW at
300kHz.
The ISL6323A provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
PVCC
BOOT
C GD
D
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
R HI1
UGATE
G
C DS
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
R LO1
R G1
R GI1
C GS
S
Q1
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
PHASE
FIGURE 18. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
C GD
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W
R HI2
R LO2
LGATE
G
R G2
R GI2
C GS
C DS
Q2
When designing the ISL6323A into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P Qg_TOT , due to the gate charge of MOSFETs and the
integrated driver ’s internal circuitry and their corresponding
average driver current can be estimated with Equations 28
and 29, respectively.
27
S
FIGURE 19. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance (P DR_UP ), the lower drive path resistance
(P DR_UP ), and in the boot strap diode (P BOOT ). The rest of
the power will be dissipated by the external gate resistors
(R G1 and R G2 ) and the internal gate resistors (R GI1 and
R GI2 ) of the MOSFETs. Figures 18 and 19 show the typical
upper and lower gate drives turn-on transition path. The total
FN6878.1
May 12, 2010
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