参数资料
| 型号： | ISL6323AIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 3/36页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR SYNC BUCK DL 48QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
第1页第2页当前第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
ISL6323A
Functional Pin Description
PIN NUMBER
1, 48
2, 47
3
4
5
6
7
8, 9
10
11
SYMBOL
FB_NB and
COMP_NB
ISEN_NB+,
ISEN_NB1-
RGND_NB
VID0/VFIXEN
VID1/SEL
VID2/SVD
VID3/SVC
VID4, VID5
VCC
FS
DESCRIPTION
These pins are the internal error amplifier inverting input and output respectively of the
NB VR controller. FB_NB, VDIFF_NB, and COMP_NB are tied together through external
R-C networks to compensate the regulator.
These pins are used for differentially sensing the North Bridge output current. The
sensed current is used for protection and load line regulation if droop is enabled.
Connect ISEN_NB- to the node between the RC sense element surrounding the inductor.
Tie the ISEN_NB+ pin to the VNB side of the sense capacitor.
This pin is an input to the NB VR controller precision differential remote-sense amplifier
and should be connected to the sense pin of the North Bridge, VDDNBFBL.
If VID1 is LO prior to enable [SVI Mode], the pin functions as the VFIXEN selection input
from the AMD processor for determining SVI mode versus VFIX mode of operation.
If VID1 is HI prior to enable [PVI Mode], the pin is used as DAC input VID0. This pin has
an internal 30μA pull-down current applied to it at all times.
This pin selects SVI or PVI mode operation based on the state of the pin prior to enabling
the ISL6323A. If the pin is LO prior to enable, the ISL6323A is in SVI mode and the dual
purpose pins [VID0/VFIXEN, VID2/SVC, VID3/SVD] use their SVI mode related
functions. If the pin held HI prior to enable, the ISL6323A is in PVI mode and dual
purpose pins use their VIDx related functions to decode the correct DAC code.
If VID1 is LO prior to enable [SVI Mode], this pin is the serial VID data bi-directional
signal to and from the master device on AMD processor. If VID1 is HI prior to enable [PVI
Mode], this pin is used to decode the programmed DAC code for the processor. In PVI
mode, this pin has an internal 30μA pull-down current applied to it. There is no pull-down
current in SVI mode.
If VID1 is LO prior to enable [SVI Mode], this pin is the serial VID clock input from the
AMD processor. If VID1 is HI prior to enable [PVI Mode], the ISL6323A is in PVI mode
and this pin is used to decode the programmed DAC code for the processor. In PVI mode,
this pin has an internal 30μA pull-down current applied to it. There is no pull-down
current in SVI mode.
These pins are active only when the ISL6323A is in PVI mode. When VID1 is HI prior to
enable, the ISL6323A decodes the programmed DAC voltage required by the AMD
processor. These pins have an internal 30μA pull-down current applied to them at all
times.
VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply
and decouple using a quality 0.1μF ceramic capacitor.
A resistor, placed from FS to Ground or from FS to VCC, sets the switching frequency of
both controllers. Refer to Equation 1 for proper resistor calculation .
R T = 10
[ 10.61 – 1.035 log ( f s ) ]
(EQ. 1)
With the resistor tied from FS to Ground, Droop is enabled. With the resistor tied from
FS to VCC, Droop is disabled.
12, 13
14
15
RGND, VSEN
OFS
DVC
3
VSEN and RGND are inputs to the core voltage regulator (VR) controller precision
differential remote-sense amplifier and should be connected to the sense pins of the
remote processor core(s), VDDFB[H,L].
The OFS pin provides a means to program a DC current for generating an offset voltage
across the resistor between FB and VSEN The offset current is generated via an external
resistor and precision internal voltage references. The polarity of the offset is selected
by connecting the resistor to GND or VCC. For no offset, the OFS pin should be left
unconnected.
The DVC pin is a buffered version of the reference to the error amplifier. A series resistor
and capacitor between the DVC pin and FB pin smooth the voltage transition during
VID-on-the-fly operations.
FN6878.1
May 12, 2010
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