参数资料
| 型号： | ISL6323AIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 30/36页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR SYNC BUCK DL 48QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6323A
2. Capture a transient event with the oscilloscope set to
about L/DCR/2 (sec/div). For example, with L = 1μH and
DCR = 1m Ω , set the oscilloscope to 500μs/div.
3. Record Δ V1 and Δ V2 as shown in Figure 21.
function, the gain of the current signal, and the value of the
compensation components, R C and C C .
C 2 (OPTIONAL)
R C
C C
COMP
Δ V 1
Δ V 2
V OUT
R FB
FB
ISL6323A
VSEN
I TRAN
FIGURE 22. COMPENSATION CONFIGURATION FOR
R 1 , NEW = R 1 , OLD ? -----------
Δ I
FIGURE 21. TIME CONSTANT MISMATCH BEHAVIOR
4. Select new values, R 1,NEW and R 2,NEW , for the time
constant resistors based on the original values, R 1,OLD
and R 2,OLD , using Equations 48 and 49.
Δ V 1
(EQ. 48)
Δ V 2
LOAD-LINE REGULATED ISL6323A CIRCUIT
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
R 2 , NEW = R 2 , OLD ? -----------
Δ V 1
Δ V 2
(EQ. 49)
Select a target bandwidth for the compensated system, f 0 .
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
5. Replace R 1 and R 2 with the new values and check to see
that the error is corrected. Repeat the procedure if
necessary.
Loadline Regulation Resistor
The loadline regulation resistor, labeled R FB in Figure 8,
sets the desired loadline required for the application.
Equation 50 can be used to calculate R FB .
per-channel switching frequency. The values of the
compensation components depend on the relationships of f 0
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
In Equation 51, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
V DROOP
R FB = ----------------------------------------------------------------------
I OUT
---------- ? -------------------------- ? --------------- ? K
R SET
3 N
MAX
400 MAX DCR
(EQ. 50)
output capacitors; ESR is the equivalent series resistance of
the bulk output filter capacitance; and V P-P is the
peak-to-peak sawtooth signal amplitude as described in the
Where R ISEN is the 2.4k Ω internal current sense resistor, K I
is defined in Equation 10 and K is defined in Equation 7.
If no loadline regulation is required, FS resistor should be
tied between the FS pin and VCC. To choose the value for
R FB in this situation, please refer to “Compensation Without
Compensation With Loadline Regulation
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
30
Once selected, the compensation values in Equation 51
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R C . Slowly increase the
value of R C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C C will not need adjustment. Keep the value of C C from
Equation 51 unless some performance issue is noted.
The optional capacitor C 2 , is sometimes needed to bypass
noise away from the PWM comparator (see Figure 22). Keep
a position available for C 2 , and be prepared to install a
high-frequency capacitor of between 22pF and 150pF in
case any leading edge jitter problem is noted.
FN6878.1
May 12, 2010
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