参数资料
| 型号： | ISL6323AIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 33/36页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR SYNC BUCK DL 48QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6323A
1k
0.3
I L (P-P) = 0
I L (P-P) = 0.25 I O
I L (P-P) = 0.5 I O
I L (P-P) = 0.75 I O
0.2
100
0.1
10
10k
100k
1M
10M
SWITCHING FREQUENCY (Hz)
FIGURE 24. R T vs SWITCHING FREQUENCY
0
0
0.2
0.4 0.6
DUTY CYCLE (V IN/ V O )
0.8
1.0
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 3-PHASE CONVERTER
0.3
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
0.2
For a four-phase design, use Figure 25 to determine the
input-capacitor RMS current requirement set by the duty
cycle, maximum sustained output current (I O ), and the ratio
of the peak-to-peak inductor current (I L(P-P) ) to I O . Select a
bulk capacitor with a ripple current rating which will minimize
the total number of input capacitors required to support the
RMS current calculated. The voltage rating of the capacitors
should also be at least 1.25x greater than the maximum input
0.1
I L (P-P) = 0
I L (P-P) = 0.5 I O
I L (P-P) = 0.75 I O
voltage. Figures 26 and 27 provide the same input RMS current
information for three-phase and two-phase designs
respectively. Use the same approach for selecting the bulk
capacitor type and number.
0
0 0.2 0.4 0.6 0.8
DUTY CYCLE (V IN/ V O )
FIGURE 27. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
1.0
0.3
I L(P-P) = 0
I L(P-P) = 0.25 I O
I L(P-P) = 0.5 I O
I L(P-P) = 0.75 I O
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the input bulk capacitors to suppress
leading and falling edge voltage spikes. The spikes result from
the high current slew rate produced by the upper MOSFET
0.2
0.1
0
0 0.2 0.4 0.6 0.8 1.0
DUTY CYCLE (V O/ V IN )
FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 4-PHASE CONVERTER
33
turn on and off. Select low ESL ceramic capacitors and place
one as close as possible to each upper MOSFET drain to
minimize board parasitics and maximize suppression.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
and lead to device overvoltage stress. Careful component
selection, layout, and placement minimizes these voltage
spikes. Consider, as an example, the turnoff transition of the
upper PWM MOSFET. Prior to turnoff, the upper MOSFET
was carrying channel current. During the turnoff, current
stops flowing in the upper MOSFET and is picked up by the
FN6878.1
May 12, 2010
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