参数资料
| 型号： | NCP345SNT1 |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/8页 |
| 文件大小： | 0K |
| 描述： | IC OVERVOLT PROT CTRLR 5TSOP |
| 产品变化通告： | Product Obsolescence 21/Jan/2010 |
| 标准包装： | 1 |
| 电压 - 工作： | 3 ~ 25V |
| 电压 - 箝位： | 7.08V |
| 技术： | 混合技术 |
| 功率（瓦特）： | 216mW |
| 电路数： | 1 |
| 应用： | 通用 |
| 封装/外壳： | 6-TSOP（0.059"，1.50mm 宽）5 引线 |
| 供应商设备封装： | 5-TSOP |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP345SNT1OSCT |
NCP345
Normal Operation
Figure 1 illustrates a typical configuration. The external
adapter provides power to the protection system so the
circuitry is only active when the adapter is connected. The
OVP monitors the voltage from the charger and if the
voltage exceeds a nominal voltage of 6.85 V, the OUT signal
drives the gate of the MOSFET to within 1.0 V of V CC , thus
turning off the FET and disconnecting the source from the
load. The nominal time it takes to drive the gate to this state
is 400 nsec (1.0 usec maximum for gate capacitance of
< 12 nF). Typical turn off performance using the CNTRL
input can be seen in Figure 6. The CNTRL input can also be
used to interrupt charging and allow the microcontroller to
measure the cell voltage under a normal condition to get a
more accurate measure of the battery voltage. Once the over
voltage is removed, the NCP345 will turn on the MOSFET.
The turn on circuitry is designed to turn on the MOSFET
more gradually to limit the in?rush current. Typical turn?on
performance is illustrated using the MGSF3441 in Figure 7.
This characteristic is a function of the threshold of the
MOSFET and will vary depending on the device
characteristics such as the gate capacitance.
The OVP has an under voltage lockout (UVLO) circuit
which disables the gate driver circuit until the UVLO senses
that the V CC voltage is above 2.6 V. Once the UVLO has
released the gate driver circuit, the OUT signal will stay high
until the voltage on the IN is sensed. If the input voltage to
IN is less than 6.85 V nominal, then the OUT signal will be
driven LOW and the FET will be turned on so the source can
be connected to the load.
There are three events that will cause the OVP to drive the
gate of the FET to a HIGH state.
? Voltage on V CC falls below the UVLO threshold
? Voltage on IN rises above 6.85 V (nominal)
? CNTRL input is driven to a logic High
http://onsemi.com
6
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