- 您现在的位置：买卖IC网 > PDF目录379698 > ATT3042-50S132I (Electronic Theatre Controls, Inc.) Field-Programmable Gate Arrays PDF资料下载
参数资料
| 型号： | ATT3042-50S132I |
| 厂商： | Electronic Theatre Controls, Inc. |
| 元件分类： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 现场可编程门阵列 |
| 文件页数： | 14/80页 |
| 文件大小： | 528K |
| 代理商： | ATT3042-50S132I |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
14
Lucent Technologies Inc.
Programmable Interconnect
(continued)
A buffer in the upper left corner of the FPGA chip drives
a global net which is available to all .k inputs of logic
blocks. Using the global buffer for a clock signal pro-
vides a skew-free, high fan-out, synchronized clock for
use at any or all of the I/O and logic blocks. Configura-
tion bits for the .k input to each logic block can select
this global line, or another routing resource, as the
clock source for its flip-flops. This net may also be pro-
grammed to drive the die edge clock lines for IOB use.
An enhanced speed, CMOS threshold, offers direct
access to this buffer and is available at the
second pad from the top of the left die edge.
A buffer in the lower right corner of the array drives a
horizontal long line that can drive programmed connec-
tions to a vertical long line in each interconnection
column. This alternate buffer also has low skew and
high fan-out. The network formed by this alternate buf-
fer’s long lines can be selected to drive the .k inputs of
the logic blocks. CMOS threshold, high-speed access
to this buffer is available from the third pad from the
bottom of the right die edge.
Internal Buses
A pair of 3-state buffers is located adjacent to each
CLB. These buffers allow logic to drive the horizontal
long lines. Logical operation of the 3-state buffer
controls allows them to implement wide multiplexing
functions. Any 3-state buffer input can be selected as
drive for the horizontal long line bus by applying a low
logic level on its 3-state control line (see Figure 15A).
The user is required to avoid contention that can result
from multiple drivers with opposing logic levels. Control
of the 3-state input by the same signal that drives the
buffer input creates an open-drain wired-AND function.
A logical high on both buffer inputs creates a high
impedance which represents no contention. A logical
low enables the buffer to drive the long line low (see
Figure 15B). Pull-up resistors are available at each end
of the long line to provide a high output when all con-
nected buffers are nonconducting. This forms fast, wide
gating functions. When data drives the inputs and sep-
arate signals drive the 3-state control lines, these buff-
ers form multiplexers (3-state buses). In this case, care
must be used to prevent contention through multiple
active buffers of conflicting levels on a common line.
Figure 16 shows 3-state buffers, long lines, and pull-up
resistors.
Figure 14. Programmable Interconnection of Long Lines
3-STATE
相关PDF资料 |
PDF描述 |
|---|---|
| ATT3042-50S44I | Field-Programmable Gate Arrays |
| ATT3042-50S68I | Field-Programmable Gate Arrays |
| ATT3042-50S84I | Field-Programmable Gate Arrays |
| ATT3042-50T132I | Field-Programmable Gate Arrays |
| ATT3042-50T44I | Field-Programmable Gate Arrays |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ATT3042-50S44I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Gate Arrays |
| ATT3042-50S68I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Gate Arrays |
| ATT3042-50S84I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Gate Arrays |
| ATT3042-50T132I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Gate Arrays |
| ATT3042-50T44I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Gate Arrays |
发布紧急采购，3分钟左右您将得到回复。