参数资料
型号: ATT3042-50S132I
厂商: Electronic Theatre Controls, Inc.
元件分类: FPGA
英文描述: Field-Programmable Gate Arrays
中文描述: 现场可编程门阵列
文件页数: 55/80页
文件大小: 528K
代理商: ATT3042-50S132I
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Lucent Technologies Inc.
55
Electrical Characteristics
(continued)
* These parameters are for clock pulses within an FPGA device. For externally applied clock, increase values by 20%.
Note: The CLB K to Q output delay (TCKO—#8) of any CLB, plus the shortest possible interconnect delay, is always longer than the data in
hold time requirement (TCKDI—#5) of any CLB on the same die.
Table 20. CLB Switching Characteristics (-50, -70, -100, and -125)
Commercial: V
CC
= 5.0 V ± 5%; 0 °C
T
A
70 °C; Industrial: V
CC
= 5.0 ± 10%, –40 °C
T
A
+85 °C.
Description
Symbol
-50
-70
-100
-125
Unit
Min
Max
14.0
Min
Max
9.0
Min
Max
7.0
Min
Max
5.5
Combinatorial Delay
Sequential Delay
Clock K to Outputs x or y
Clock K to Outputs x or y when Q
Returned Through Function
Generators F or G to Drives x or y
Setup Time
Logic Variables
Data In
Enable Clock
Reset Direct Active
Hold Time
Logic Variables
Data In
Enable Clock
Clock
High Time*
Low Time*
Flip-Flop Toggle Rate*
Reset Direct (rd)
rd Width
Delay from rd to Outputs x, y
Master Reset (MR)
MR Width
Delay from MR to Outputs x, y
1
T
ILO
ns
8
T
CKO
T
QLO
12.0
23.0
6.0
13.0
5.0
10.0
4.5
8.0
ns
ns
2
4
6
T
ICK
T
DICK
T
ECCK
T
RDCK
12.0
8.0
10.0
1.0
8.0
5.0
7.0
1.0
7.0
4.0
5.0
1.0
5.5
3.0
4.5
1.0
ns
ns
ns
ns
3
5
7
T
CKI
T
CKDI
T
CKEC
1.0
6.0
0
0
4.0
0
0
2.0
0
0
1.5
0
ns
ns
ns
11
12
T
CH
T
CL
F
CLK
9.0
9.0
50
5.0
5.0
70
4.0
4.0
100
3.0
3.0
125
ns
ns
MHz
13
9
T
RPW
T
RIO
12.0
12.0
8.0
8.0
7.0
7.0
6.0
6.0
ns
ns
T
MRW
T
MRQ
30
27
25
23
21
19
20
17
ns
ns
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