参数资料
型号: ATT3042-50S132I
厂商: Electronic Theatre Controls, Inc.
元件分类: FPGA
英文描述: Field-Programmable Gate Arrays
中文描述: 现场可编程门阵列
文件页数: 66/80页
文件大小: 528K
代理商: ATT3042-50S132I
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
66
Lucent Technologies Inc.
Electrical Characteristics
(continued)
Figure 39. Slave Mode Switching Characteristics
Notes:
The maximum limit of CCLK LOW time is caused by dynamic circuitry inside the FPGA device.
Configuration must be delayed until the
INIT
of all FPGAs is high.
At powerup, V
CC
must rise from 2.0 V to V
CC
minimum in less than 25 ms. If this is not possible, configuration can be delayed by holding
RESET
low until V
CC
has reached 4.0 V. A very long V
CC
rise time of >100 ms, or a nonmonotonically rising V
CC
, may require a >1 μs high level on
RESET
, followed by >6 μs low level on
RESET
and D/
P
after V
CC
has reached 4.0 V.
Table 29. Slave Mode Switching Characteristics
Commercial: V
CC
= 5.0 V ± 5%; 0 °C
T
A
70 °C; Industrial: V
CC
= 5.0 ± 10%, –40 °C
T
A
+85 °C.
Signal
Description
Symbol
Min
Max
Unit
CCLK
To DOUT
DIN Setup
DIN Hold
HIGH Time
LOW Time
Frequency
3
1
2
4
5
T
CCO
T
DCC
T
CCD
T
CCH
T
CCL
F
CC
60
0
0.05
0.05
100
5.0
10.0
ns
ns
ns
μs
μs
MHz
T
DCC
DIN
CCLK
DOUT
(OUTPUT)
T
CCD
BIT N
T
CCH
BIT N – 1
BIT N + 1
T
CCL
BIT N
T
CCO
1
2
4
5
3
5-3130(F)
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