参数资料
型号: MAX6316LUK29AX-T
厂商: Maxim Integrated Products
文件页数: 7/14页
文件大小: 0K
描述: IC MPU/RESET CIRC 2.93V SOT23-5
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 1 ms
电压 - 阀值: 2.93V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SC-74A,SOT-753
供应商设备封装: SOT-23-5
包装: 带卷 (TR)
MAX6316–MAX6322
5-Pin μP Supervisory Circuits with
Watchdog and Manual Reset
Bidirectional R E S E T Output
The MAX6316M/MAX6318MH/MAX6319MH are designed
to interface with μPs that have bidirectional reset pins,
such as the Motorola 68HC11. Like an open-drain output,
these devices allow the μP or other devices to pull the
bidirectional reset ( RESET ) low and assert a reset condi-
tion. However, unlike a standard open-drain output, it
includes the commonly specified 4.7k ? pullup resistor
with a P-channel active pullup in parallel.
This configuration allows the MAX6316M/MAX6318MH/
MAX6319MH to solve a problem associated with μPs
that have bidirectional reset pins in systems where sev-
eral devices connect to RESET (Figure 3). These μPs
can often determine if a reset was asserted by an exter-
nal device (i.e., the supervisor IC) or by the μP itself
(due to a watchdog fault, clock error, or other source),
and then jump to a vector appropriate for the source of
the reset. However, if the μP does assert reset, it does
not retain the information, but must determine the
cause after the reset has occurred.
The following procedure describes how this is done in
the Motorola 68HC11. In all cases of reset, the μP pulls
RESET low for about four external-clock cycles. It then
releases RESET , waits for two external-clock cycles,
then checks RESET ’s state. If RESET is still low, the μP
concludes that the source of the reset was external
and, when RESET eventually reaches the high state, it
jumps to the normal reset vector. In this case, stored-
state information is erased and processing begins from
scratch. If, on the other hand, RESET is high after a
delay of two external-clock cycles, the processor
knows that it caused the reset itself and can jump to a
different vector and use stored-state information to
determine what caused the reset.
A problem occurs with faster μPs; two external-clock
cycles are only 500ns at 4MHz. When there are several
devices on the reset line, and only a passive pullup resis-
tor is used, the input capacitance and stray capacitance
can prevent RESET from reaching the logic high state (0.8
  V CC ) in the time allowed. If this happens, all resets will
be interpreted as external. The μP output stage is guaran-
teed to sink 1.6mA, so the rise time can not be reduced
considerably by decreasing the 4.7k ? internal pullup
resistance. See Bidirectional Pullup Characteristics in the
Typical Operating Characteristics.
The MAX6316M/MAX6318MH/MAX6319MH overcome
this problem with an active pullup FET in parallel with the
4.7k ? resistor (Figures 4 and 5). The pullup transistor
holds RESET high until the μP reset I/O or the supervisory
circuit itself forces the line low. Once RESET goes below
V PTH , a comparator sets the transition edge flip-flop, indi-
cating that the next transition for RESET will be low to
high. When RESET is released, the 4.7k ? resistor pulls
RESET up toward V CC . Once RESET rises above V PTH
but is below (0.85 x V CC ), the active P-channel pullup
turns on. Once RESET rises above (0.85 x V CC ) or the
2μs one-shot times out, the active pullup turns off. The
parallel combination of the 4.7k ? pullup and the
V CC
V CC
WDI*
4.7k ?
68HC11
MR**
RESET
CIRCUITRY
RESET
RESET
RESET
RESET***
CIRCUITRY
MAX6316M
MAX6318MH
MAX6319MH
C IN
C STRAY
RESET
C IN
* MAX6316M/MAX6318MH
C IN
OTHER DEVICES
** MAX6316M/MAX6319MH
*** ACTIVE-HIGH PUSH/PULL MAX6318MH/MAX6319MH
Figure 3. MAX6316M/MAX6318MH/MAX6319MH Supports Additional Devices on the Reset Bus
Maxim Integrated
7
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