参数资料
| 型号： | LT1965EQ-3.3#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 13/22页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 3.3V 1.1A 5-DDPAK |
| 产品培训模块： | More Information on LDOs |
| 标准包装： | 50 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 3.3V |
| 输入电压： | 最高 20V |
| 电压 - 压降（标准）： | 0.31V @ 1.1A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 1.1A |
| 电流 - 限制（最小）： | 1.2A |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-263-6，D²Pak（5 引线+接片），TO-263BA |
| 供应商设备封装： | D2PAK-5 |
| 包装： | 管件 |
| 产品目录页面： | 1330 (CN2011-ZH PDF) |
LT1965 Series
APPLICATIONS INFORMATION
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or micro-
phone works. For a ceramic capacitor, the stress can be
induced by vibrations in the system or thermal transients.
The resulting voltages produced can cause appreciable
amounts of noise. A ceramic capacitor produced the trace
in Figure 5 in response to light tapping from a pencil.
Similar vibration induced behavior can masquerade as
increased output voltage noise.
Overload Recovery
Like many IC power regulators, the LT1965 has safe oper-
ating area protection. The safe area protection decreases
current limit as input-to-output voltage increases and keeps
the power transistor inside a safe operating region for all
values of input-to-output voltage. The protective design
provides some output current at all values of input-to-
output voltage up to the device breakdown.
When power is first applied, as input voltage rises, the
output follows the input, allowing the regulator to start up
into very heavy loads. During start-up, as the input voltage
20
0
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
40
20
–20
X5R
0
X5R
–20
–40
–40
Y5V
–60
Y5V
–60
–80
–80
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
–100
0
2
4
6
8
10
12
14
16
–100
–50 –25
0
25
50
75
100
125
DC BIAS VOLTAGE (V)
1965 F03
TEMPERATURE (°C)
1965 F04
Figure 3. Ceramic Capacitor DC Bias Characteristics
1mV/DIV
Figure 4. Ceramic Capacitor Temperature Characteristics
V OUT = 1.3V
C OUT = 10μF
I LOAD = 0
1ms/DIV
1965 F05
Figure 5. Noise Resulting from Tapping on a Ceramic Capacitor
13
For more information www.linear.com/LT1965
1965fb
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