参数资料
| 型号： | ISL6333CRZ |
| 厂商： | Intersil |
| 文件页数： | 25/40页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 3PHASE BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR11 |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页当前第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页
ISL6333, ISL6333A, ISL6333B, ISL6333C
In Equation 10, V REF is the reference voltage, V OFS is the
programmed offset voltage, I OUT is the total output current of
VDIFF
the converter, R ISEN is the internal sense resistor connected
-
ISL6333 INTERNAL CIRCUIT
to the ISEN+ pin, R FB is the feedback resistor, N is the active
number of channels, and DCR is the Inductor DCR value.
V OFS
+
R FB
VREF
E/A
Therefore the equivalent loadline impedance, i.e. droop
impedance, is equal to Equation 11:
I OFS
FB
R LL = ------------ ? --------------- ? ----------
R SET
R FB DCR 400
N 3
Output-Voltage Offset Programming
(EQ. 11)
VCC
The controllers allow the designer to accurately adjust the
offset voltage by connecting a resistor, R OFS , from the OFS
pin to VCC or GND. When R OFS is connected between OFS
R OFS
+
-
+
1.6V
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I OFS ) to flow into the OFS pin
and out of the FB pin, providing a negative offset. If R OFS is
OFS
-
GND
0.3V
VCC
connected to ground, the voltage across it is regulated to
0.3V, and I OFS flows into the FB pin and out of the OFS pin,
providing a positive offset. The offset current flowing through
the resistor between VSEN and FB will generate the desired
offset voltage which is equal to the product (I OFS x R FB ).
These functions are shown in Figures 8 and 9.
VDIFF
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the controllers
to do this by making changes to the VID inputs. The
controllers are required to monitor the DAC inputs and
+
V OFS
-
R FB
FB
I OFS
ISL6333 INTERNAL CIRCUIT
VREF
E/A
respond to on-the-fly VID changes in a controlled manner,
supervising a safe output voltage transition without
discontinuity or disruption.
The controllers check for VID changes by comparing the
internal DAC code to the VID pin inputs on the positive edge
of an internal 5.55MHz clock. If a new code is established on
the VID inputs and it remains stable for 3 consecutive
readings (360ns to 540ns), the controllers recognize the new
code and begins incrementing/decrementing the DAC in
6.25mV steps at a stepping frequency of 1.85MHz. This
controlled slew rate of 6.25mV/540ns (11.6mV/μs) continues
-
1.6V
until the VID input and DAC are equal. Thus, the total time
OFS
+
-
0.3V
+
required for a VID change, t DVID , is dependent only on the size
of the VID change ( Δ V VID ).
R OFS
The time required for a ISL6333-based converter to make a
GND
GND
VCC
1.6V to 0.5V reference voltage change is about 95μs, as
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
calculated using Equation 14.
– 9 ? Δ V VID ?
? 0.00625 ?
PROGRAMMING
Once the desired output offset voltage has been determined,
t DVID = 540 ? 10
? ---------------------
(EQ. 14)
use Equations 12 and 13 to set R OFS :
VID “Off” DAC Codes
R OFS = --------------------------
For Negative Offset (connect R OFS to VCC):
1.6 ? R FB
V OFFSET
(EQ. 12)
The Intel VR11 VID tables include “Off” DAC codes, which
indicate to the controllers to disable all regulation. Recognition
of these codes is slightly different in that they must be stable for
4 consecutive readings of a 5.55MHz clock (540ns to 720ns)
to be recognized. Once an “Off” code is recognized the
R OFS = --------------------------
For Positive Offset (connect R OFS to GND):
0.3 ? R FB
V OFFSET
25
(EQ. 13)
controllers latch off, and must be reset by toggling the EN pin.
FN6520.3
October 8, 2010
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