参数资料
| 型号： | ISL6333CRZ |
| 厂商： | Intersil |
| 文件页数： | 29/40页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 3PHASE BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR11 |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6333, ISL6333A, ISL6333B, ISL6333C
ramp times, t d2 and t d4 , can be calculated based on
Equations 20 and 21:
voltage within the proper levels, and whether any fault
conditions exist. This pin should be tied through a resistor to
t d2 = 1.1 ? R SS ? 8 ? 10
– 3
( μ s )
(EQ. 20)
a voltage source that’s equal to or less then VCC.
(EQ. 21)
t d4 = V VID – 1.1 ? R SS ? 8 ? 10
( μ s )
– 3
For example, when VID is set to 1.5V and the R SS is set at
100k Ω , the first soft-start ramp time t d2 will be 880μs and the
second soft-start ramp time t d4 will be 320μs.
I AVG
100μA
+
OCP
-
+ I 1
OCL
- 140μA
REPEAT FOR
EACH CHANNEL
After the DAC voltage reaches the final VID setting, VR_RDY
will be set to high with the fixed delay t d5 . The typical value for
t d5 is 93μs.
DAC
+175mV
+
OCP
-
IMON
V OCP
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
1.280V
SOFT-START, FAULT
AND CONTROL LOGIC
BELOW DAC LEVEL
-
OVP
GND>
V OUT (0.5V/DIV)
+
VR_RDY
VDIFF
-
GND>
EN (5V/DIV)
0.50xDAC
+
UV
t1 t2
t3
ISL6333 INTERNAL CIRCUITRY
FIGURE 17. SOFT-START WAVEFORMS FOR ISL6333-BASED
MULTI-PHASE CONVERTER
Pre-Biased Soft-Start
The controllers also have the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output to
ramp from the pre-charged level to the final level dictated by
the DAC setting. Should the output be pre-charged to a level
exceeding the DAC setting, the output drives are enabled at
the end of the soft-start period, leading to an abrupt correction
FIGURE 18. POWER GOOD AND PROTECTION CIRCUITRY
VR_RDY indicates whether VDIFF is within specified
overvoltage and undervoltage limits after a fixed delay from the
end of soft-start. VR_RDY transitions low when an
undervoltage, overvoltage, or overcurrent condition is detected
or when the controllers are disabled by a reset from EN, POR,
or one of the no-CPU VID codes. In the event of an overvoltage
or overcurrent condition, or a no-CPU VID code, the controllers
latch off and VR_RDY will not return high until EN is toggled
and a successful soft-start is completed. In the case of an
undervoltage event, VR_RDY will return high when the output
voltage rises above the undervoltage hysteresis level. VR_RDY
is always low prior to the end of soft-start.
in the output voltage down to the DAC-set level.
Overvoltage Protection
Fault Monitoring and Protection
The controllers actively monitor the output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common VR_RDY indicator is provided for linking to external
system monitors. The schematic in Figure 18 outlines the
interaction between the fault monitors and the VR_RDY signal.
The controllers constantly monitor the difference between the
VSEN and RGND voltages to detect if an overvoltage event
occurs. During soft-start, while the DAC is ramping up, the
overvoltage trip level is the higher of a fixed voltage 1.280V or
DAC + 175mV. Upon successful soft-start, the overvoltage trip
level is only DAC + 175mV. When the output voltage rises
above the OVP trip level actions are taken by the controllers to
protect the microprocessor load.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output that signals
whether or not the controllers are regulating the output
29
At the inception of an overvoltage event, LGATE1, LGATE2,
and LGATE3 are commanded high and the VR_RDY signal
is driven low. This turns on the all of the lower MOSFETs and
FN6520.3
October 8, 2010
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