参数资料
| 型号： | ISL6333CRZ |
| 厂商： | Intersil |
| 文件页数： | 35/40页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 3PHASE BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR11 |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6333, ISL6333A, ISL6333B, ISL6333C
In Equation 40, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent series resistance of
C 2
the bulk output filter capacitance; and V P-P is the
R C
C C
COMP
peak-to-peak sawtooth signal amplitude, as described in the
FB
Once selected, the compensation values in Equation 40
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R C . Slowly increase the
value of R C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C C will not need adjustment. Keep the value of C C from
C 1
R 1
R FB
VSEN
ISL6333
Equation 40 unless some performance issue is noted.
The optional capacitor C 2 , is sometimes needed to bypass
noise away from the PWM comparator (see Figure 24). Keep
a position available for C 2 , and be prepared to install a
high-frequency capacitor of between 22pF and 150pF in
case any leading edge jitter problem is noted.
FIGURE 25. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f 0 , of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f HF . This pole can be used for
-------------------------------- > f 0
2 ? π ? f 0 ? V P-P ? L ? C
R C = R FB ? ----------------------------------------------------------
2 ? π ? V P-P ? R FB ? f 0
R 1 = R FB ? --------------------------------------------
Case 1:
1
2 ? π ? L ? C
V IN
V IN
C C = ------------------------------------------------------
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose f HF = 10f 0 , but it can be
higher if desired. Choosing f HF to be lower than 10f 0 can
cause problems with too much phase shift below the system
bandwidth.
C ? ESR
L ? C – C ? ESR
-------------------------------- ≤ f 0 < -------------------------------------
V PP ? ( 2 ? π ) 2 ? f 02 ? L ? C
C C = ---------------------------------------------------------------------------------------
P-P ? R FB ?
( 2 ? π ) 2 ? f 2 ? V L ? C
C 1 = --------------------------------------------
( 2 ? π ) 2 ? f 0 ? f HF ? ( L ? C ) ? R FB ? V P-P
V PP ? ? 2 π ? ? f 0 ? f HF ? L ? C ? R FB
R C = -----------------------------------------------------------------------------------------
Case 2:
1 1
2 ? π ? L ? C 2 ? π ? C ? ESR
V
R C = R FB ? -----------------------------------------------------------------
IN
V IN
0
(EQ. 40)
L ? C – C ? ESR
R FB
V IN
C 2 = -----------------------------------------------------------------------------------------------------
2
? ?
V IN ? ( 2 ? π ? f HF ? L ? C – 1 )
(EQ. 41)
f 0 > -------------------------------------
R C = R FB ? ----------------------------------------------
2 ? π ? V P-P ? R FB ? f 0 ? L
( 2 ? π ) 2 ? f 0 ? f HF ? ( L ? C ) ? R FB ? V P-P
Case 3:
1
2 ? π ? C ? ESR
2 ? π ? f 0 ? V P-P ? L
V IN ? ESR
V IN ? ESR ? C
C C = ------------------------------------------------------------------
V IN ? ( 2 ? π ? f HF ? L ? C – 1 )
C C = -----------------------------------------------------------------------------------------------------
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 41, R FB is selected arbitrarily. The remaining
compensation components are then selected.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 25, provides the
necessary compensation.
35
In Equation 41, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V P-P is the
peak-to-peak sawtooth signal amplitude, as described in the
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
FN6520.3
October 8, 2010
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