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参数资料
| 型号： | CAT1022LI-45-G |
| 厂商： | ON Semiconductor |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISR CPU 2K EEPROM 8PDIP |
| 标准包装： | 50 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 130 ms |
| 电压 - 阀值： | 4.5V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
CAT1021, CAT1022, CAT1023
EMBEDDED EEPROM OPERATON
The CAT1021/22/23 feature a 2 ? kbit embedded serial
EEPROM that supports the I 2 C Bus data transmission
protocol. This Inter ? Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
Both the Master device and Slave device can operate as
either transmitter or receiver, but the Master device controls
which mode is activated.
I 2 C Bus Protocol
The features of the I 2 C bus protocol are defined as
follows:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
Start Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT1021/22/23 monitor the SDA
and SCL lines and will not respond until this condition is
met.
Stop Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant bits
of the 8 ? bit slave address are programmable in metal and the
default is 1010.
The last bit of the slave address specifies whether a Read
or Write operation is to be performed. When this bit is set to
1, a Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT1021/22/23 monitors the bus and
responds with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
CAT1021/22/23 then perform a Read or Write operation
depending on the R/W bit.
SCL
tF
tLOW
tHIGH
tLOW
tR
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
tBUF
SDA OUT
Figure 3. Bus Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
Figure 4. Write Cycle Timing
http://onsemi.com
9
START
CONDITION
ADDRESS
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT1022LI-45-GT2 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer |
| CAT1022LI-45-GT3 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer |
| CAT1022LI-45T2 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer |
| CAT1022LI-45-T2 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer |
| CAT1022LI-45T3 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer |
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