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参数资料
| 型号： | CAT24C21PE |
| 元件分类： | PROM |
| 英文描述： | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封装： | PLASTIC, DIP-8 |
| 文件页数： | 11/12页 |
| 文件大小： | 65K |
| 代理商： | CAT24C21PE |
CAT24C21
8
Doc. No. 1032, Rev. N
Figure 10. Page Write Timing
Figure 9. Byte Write Timing
nMAX = 7FH
P = 15 for CAT24WC21
* = Don't care
Write Protection
When the VCLK pin is connected to GND and the
CAT24C21 is in the bi-directional mode, the entire
memory is protected and becomes "read only".
Read Operations
The READ operation for the CAT24C21 is initiated in the
same manner as the write operation with the one
exception that the R/
W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
The CAT24C21’s address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to address
N, the READ immediately following would access data
from address N + 1 (Figure 11). If N = 127, then the
counter will 'wrap around' to address 0 and continue to
clock out data.
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+P
BYTE
ADDRESS (n)
A
C
K
A
C
K
DATA n
A
C
K
S
T
O
P
S
A
C
K
DATA n+1
A
C
K
S
T
A
R
T
P
SLAVE
ADDRESS
*
** *
BYTE
ADDRESS
SLAVE
ADDRESS
S
A
C
K
A
C
K
DATA
A
C
K
S
T
O
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
** *
*
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation (Figure 12). The Master device first performs
a ‘dummy’ write operation by sending the START
condition, slave address and byte address of the location
it wishes to read. After the CAT24C21 acknowledges the
word address, the Master device resends the START
condition and the slave address, this time with the R/
W
bit set to one. The CAT24C21 then responds with its
ACK and sends the 8-bit byte requested. The master
device does not send an ACK but will generate a STOP
condition.
Sequential Read
The Sequential READ operation (Figure 13) can be
initiated by either the Immediate Address READ or the
Selective READ operation. After the CAT24C21 sends
the first 8-bit byte, the Master responds with an ACK,
which tells the Slave that more data is being requested.
The CAT24C21 will continue to output an 8-bit byte for
each ACK sent by the Master. The entire memory
content can thus be read out sequentially. If the end of
memory is reached in the process, then addressing will
'wrap-around' to the beginning of memory. Data output
will stop when the Master fails to acknowledge and
sends a STOP condition.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT24C21WGI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT24C21WGI-T3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT24C21WI | 功能描述:电可擦除可编程只读存储器 1K Dual Mode Serial RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| CAT24C21WI-G | 制造商:Rochester Electronics LLC 功能描述: 制造商:ON Semiconductor 功能描述: |
| CAT24C21WI-GT3 | 功能描述:电可擦除可编程只读存储器 1K DUAL MODE SER 电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
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